gpu: nvgpu: move runlist update timeout rc to common/rc

Move runlist update timeout recovery from runlist.c to
rc.c
Move RC_TYPE defines from fifo.h to rc.h

JIRA NVGPU-1314

Change-Id: I66925ca9fba904c523be69ad99808e3de33a7d46
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093666
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/fifo/runlist.c

@@ -26,6 +26,7 @@
 #include <nvgpu/runlist.h>
 #include <nvgpu/bug.h>
 #include <nvgpu/dma.h>
+#include <nvgpu/rc.h>
 
 void nvgpu_fifo_lock_active_runlists(struct gk20a *g)
 {
@@ -466,16 +467,6 @@ int nvgpu_fifo_reschedule_runlist(struct channel_gk20a *ch, bool preempt_next,
 	return ret;
 }
 
-static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id)
-{
-	u32 engines = g->ops.fifo.runlist_busy_engines(g, runlist_id);
-
-	if (engines != 0U) {
-		gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true,
-				RC_TYPE_RUNLIST_UPDATE_TIMEOUT);
-	}
-}
-
 /* add/remove a channel from runlist
    special cases below: runlist->active_channels will NOT be changed.
    (ch == NULL && !add) means remove all active channels from runlist.
@@ -509,7 +500,7 @@ static int gk20a_runlist_update(struct gk20a *g, u32 runlist_id,
 	nvgpu_mutex_release(&runlist->runlist_lock);
 
 	if (ret == -ETIMEDOUT) {
-		gk20a_fifo_runlist_reset_engines(g, runlist_id);
+		nvgpu_rc_runlist_update(g, runlist_id);
 	}
 
 	return ret;

drivers/gpu/nvgpu/common/fifo/tsg.c

@@ -27,6 +27,7 @@
 #include <nvgpu/os_sched.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/tsg.h>
+#include <nvgpu/rc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/error_notifier.h>
 #include <nvgpu/gr/config.h>

drivers/gpu/nvgpu/common/rc/rc.c

@@ -84,4 +84,14 @@ void nvgpu_rc_pbdma_fault(struct gk20a *g, struct fifo_gk20a *f,
 	} else {
 		nvgpu_err(g, "Invalid pbdma_status.id_type");
 	}
-}
+}
+
+void nvgpu_rc_runlist_update(struct gk20a *g, u32 runlist_id)
+{
+	u32 eng_bitmask = g->ops.fifo.runlist_busy_engines(g, runlist_id);
+
+	if (eng_bitmask != 0U) {
+		gk20a_fifo_recover(g, eng_bitmask, INVAL_ID, false, false, true,
+				RC_TYPE_RUNLIST_UPDATE_TIMEOUT);
+	}
+}

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -41,6 +41,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/rc.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>

drivers/gpu/nvgpu/gk20a/gr_gk20a.c

@@ -41,6 +41,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/rc.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>
 #include <nvgpu/string.h>

drivers/gpu/nvgpu/gv11b/fifo_gv11b.c

@@ -40,6 +40,7 @@
 #include <nvgpu/io.h>
 #include <nvgpu/utils.h>
 #include <nvgpu/fifo.h>
+#include <nvgpu/rc.h>
 #include <nvgpu/runlist.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/channel.h>

drivers/gpu/nvgpu/hal/fb/fb_gv11b.c

@@ -38,6 +38,7 @@
 #include <nvgpu/channel.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/ltc.h>
+#include <nvgpu/rc.h>
 
 #include "gk20a/mm_gk20a.h"
 

drivers/gpu/nvgpu/hal/fifo/fifo_intr_gv11b.c

@@ -29,12 +29,12 @@
 #include <nvgpu/tsg.h>
 #include <nvgpu/nvgpu_err.h>
 #include <nvgpu/error_notifier.h>
+#include <nvgpu/rc.h>
 
 #include <hal/fifo/fifo_intr_gk20a.h>
 #include <hal/fifo/fifo_intr_gv11b.h>
 
 #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h>
-#include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> /* TODO: remove */
 
 static const char *const gv11b_sched_error_str[] = {
 	"xxx-0",

drivers/gpu/nvgpu/include/nvgpu/fifo.h

@@ -25,16 +25,6 @@
 #ifndef NVGPU_FIFO_COMMON_H
 #define NVGPU_FIFO_COMMON_H
 
-#define RC_TYPE_NO_RC			0U
-#define RC_TYPE_MMU_FAULT		1U
-#define RC_TYPE_PBDMA_FAULT		2U
-#define RC_TYPE_GR_FAULT		3U
-#define RC_TYPE_PREEMPT_TIMEOUT		4U
-#define RC_TYPE_CTXSW_TIMEOUT		5U
-#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT	6U
-#define RC_TYPE_FORCE_RESET		7U
-#define RC_TYPE_SCHED_ERR		8U
-
 #define INVAL_ID			(~U32(0U))
 
 #define CTXSW_TIMEOUT_PERIOD_MS		100U

drivers/gpu/nvgpu/include/nvgpu/rc.h

@@ -25,6 +25,18 @@
 
 #include <nvgpu/types.h>
 
+#define RC_TYPE_NO_RC			0U
+#define RC_TYPE_MMU_FAULT		1U
+#define RC_TYPE_PBDMA_FAULT		2U
+#define RC_TYPE_GR_FAULT		3U
+#define RC_TYPE_PREEMPT_TIMEOUT		4U
+#define RC_TYPE_CTXSW_TIMEOUT		5U
+#define RC_TYPE_RUNLIST_UPDATE_TIMEOUT	6U
+#define RC_TYPE_FORCE_RESET		7U
+#define RC_TYPE_SCHED_ERR		8U
+
+#define INVAL_ID			(~U32(0U))
+
 struct gk20a;
 struct tsg_gk20a;
 struct fifo_gk20a;
@@ -35,4 +47,6 @@ void nvgpu_rc_ctxsw_timeout(struct gk20a *g, u32 eng_bitmask,
 void nvgpu_rc_pbdma_fault(struct gk20a *g, struct fifo_gk20a *f,
 			u32 pbdma_id, u32 error_notifier);
 
+void nvgpu_rc_runlist_update(struct gk20a *g, u32 runlist_id);
+
 #endif /* NVGPU_RC_H */