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gpu: nvgpu: SEC2 RTOS interface headers

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-Created command/message nv_flcn_cmd/msg_sec2
 data struct to communicate between nvgpu<->sec2-rtos
 in header file sec2_cmd_if.h
-Created acr command/message nv_sec2_acr_cmd/msg
 to perform operation like bootstrap LSF flacon
 in header file sec2_if_acr.h
-Created defines common SEC2 defines to use across
 multiple operation related to SEC2-RTOS in header file
 sec2_if_cmn.h
-Created data struct sec2_init_msg_sec2_init to receive
 message from SEC2-RTOS to init queues, debug
 data in header file sec2_if_sec2.h

JIRA NVGPUT-81

Change-Id: I4efbca20de7a2483d17de97841ada5336189e2b8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2018-09-17 10:16:51 +05:30
committed by mobile promotions
parent 3bbd40366a
commit 18f80ca25c
5 changed files with 296 additions and 0 deletions
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2
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
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@@ -96,6 +96,8 @@ struct pmu_hdr {
u8 seq_id;
};
#define NV_FLCN_UNIT_ID_REWIND (0x00U)
#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr)

50
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_cmd_if.h Normal file
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@@ -0,0 +1,50 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_CMD_IF_H
#define NVGPU_SEC2_CMD_IF_H
#include <nvgpu/sec2if/sec2_if_sec2.h>
#include <nvgpu/sec2if/sec2_if_acr.h>
struct nv_flcn_cmd_sec2 {
struct pmu_hdr hdr;
union {
union nv_sec2_acr_cmd acr;
} cmd;
};
struct nv_flcn_msg_sec2 {
struct pmu_hdr hdr;
union {
union nv_flcn_msg_sec2_init init;
union nv_sec2_acr_msg acr;
} msg;
};
#define NV_SEC2_UNIT_REWIND NV_FLCN_UNIT_ID_REWIND
#define NV_SEC2_UNIT_INIT (0x01U)
#define NV_SEC2_UNIT_ACR (0x07U)
#define NV_SEC2_UNIT_END (0x0AU)
#endif /* NVGPU_SEC2_CMD_IF_H */

96
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_acr.h Normal file
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@@ -0,0 +1,96 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_IF_ACR_H
#define NVGPU_SEC2_IF_ACR_H
#include <nvgpu/types.h>
/*
* ACR Command Types
* _BOOT_FALCON
* NVGPU sends a Falcon ID and LSB offset to SEC2 to boot
* the falcon in LS mode.
* SEC2 needs to hanlde the case since UCODE of falcons are
* stored in secured location on FB.
*/
#define NV_SEC2_ACR_CMD_ID_BOOTSTRAP_FALCON 0U
/* nvgpu provides the Falcon ID to bootstrap */
struct nv_sec2_acr_cmd_bootstrap_falcon {
/* Command must be first as this struct is the part of union */
u8 cmd_type;
/* Additional bootstrapping flags */
u32 flags;
/* ID to identify Falcon, ref LSF_FALCON_ID_<XYZ> */
u32 falcon_id;
};
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET 0U
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1U
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0U
/* A union of all ACR Commands */
union nv_sec2_acr_cmd {
/* Command type */
u8 cmd_type;
/* Bootstrap Falcon */
struct nv_sec2_acr_cmd_bootstrap_falcon bootstrap_falcon;
};
/* ACR Message Status */
/* Returns the Bootstrapped falcon ID to RM */
#define NV_SEC2_ACR_MSG_ID_BOOTSTRAP_FALCON 0U
/* Returns the Error Status for Invalid Command */
#define NV_SEC2_ACR_MSG_ID_INVALID_COMMAND 2U
/*
* SEC2 notifies nvgpu about bootstrap status of falcon
*/
struct nv_sec2_acr_msg_bootstrap_falcon {
/* Message must be at start */
u8 msg_type;
/* Falcon Error Code returned by message */
u32 error_code;
/* Bootstrapped falcon ID by ACR */
u32 falcon_id;
} ;
/*
* A union of all ACR Messages.
*/
union nv_sec2_acr_msg {
/* Message type */
u8 msg_type;
/* Bootstrap details of falcon and status code */
struct nv_sec2_acr_msg_bootstrap_falcon msg_flcn;
};
#endif /* NVGPU_SEC2_IF_ACR_H */

73
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_cmn.h Normal file
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@@ -0,0 +1,73 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_IF_CMN_H
#define NVGPU_SEC2_IF_CMN_H
/*
* Define the maximum number of command sequences that can be in flight at
* any given time. This is dictated by the width of the sequence number
* id ('seqNumId') stored in each sequence packet (currently 8-bits).
*/
#define NV_SEC2_MAX_NUM_SEQUENCES 256U
/*
* Compares an unit id against the values in the unit_id enumeration and
* verifies that the id is valid. It is expected that the id is specified
* as an unsigned integer.
*/
#define NV_SEC2_UNITID_IS_VALID(id) (((id) < NV_SEC2_UNIT_END))
/*
* Defines the size of the surface/buffer that will be allocated to store
* debug spew from the SEC2 ucode application when falcon-trace is enabled.
*/
#define NV_SEC2_DEBUG_SURFACE_SIZE (32U*1024U)
/*
* SEC2's frame-buffer interface block has several slots/indices which can
* be bound to support DMA to various surfaces in memory. This is an
* enumeration that gives name to each index based on type of memory-aperture
* the index is used to access.
*
* Pre-Turing, NV_SEC2_DMAIDX_PHYS_VID_FN0 == NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND.
* From Turing, engine context is stored in GPA, requiring a separate aperture.
*
* Traditionally, video falcons have used the 6th index for ucode, and we will
* continue to use that to allow legacy ucode to work seamlessly.
*
* Note: DO NOT CHANGE THE VALUE OF NV_SEC2_DMAIDX_UCODE. That value is used by
* both the legacy SEC2 ucode, which assumes that it will use index 6, and by
* SEC2 RTOS. Changing it will break legacy SEC2 ucode, unless it is updated to
* reflect the new value.
*/
#define NV_SEC2_DMAIDX_GUEST_PHYS_VID_BOUND 0U
#define NV_SEC2_DMAIDX_VIRT 1U
#define NV_SEC2_DMAIDX_PHYS_VID_FN0 2U
#define NV_SEC2_DMAIDX_PHYS_SYS_COH_FN0 3U
#define NV_SEC2_DMAIDX_PHYS_SYS_NCOH_FN0 4U
#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_COH_BOUND 5U
#define NV_SEC2_DMAIDX_UCODE 6U
#define NV_SEC2_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND 7U
#endif /* NVGPU_SEC2_IF_CMN_H */

75
drivers/gpu/nvgpu/include/nvgpu/sec2if/sec2_if_sec2.h Normal file
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@@ -0,0 +1,75 @@
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SEC2_IF_SEC2_H
#define NVGPU_SEC2_IF_SEC2_H
/*
* SEC2 Command/Message Interfaces - SEC2 Management
*/
/*
* Defines the identifiers various high-level types of sequencer commands and
* messages.
* _SEC2_INIT - sec2_init_msg_sec2_init
*/
enum
{
NV_SEC2_INIT_MSG_ID_SEC2_INIT = 0U,
};
/*
* Defines the logical queue IDs that must be used when submitting commands
* to or reading messages from SEC2. The identifiers must begin with zero and
* should increment sequentially. _CMDQ_LOG_ID__LAST must always be set to the
* last command queue identifier. _NUM must always be set to the last
* identifier plus one.
*/
#define SEC2_NV_CMDQ_LOG_ID 0U
#define SEC2_NV_CMDQ_LOG_ID__LAST 0U
#define SEC2_NV_MSGQ_LOG_ID 1U
#define SEC2_QUEUE_NUM 2U
struct sec2_init_msg_sec2_init {
u8 msg_type;
u8 num_queues;
u16 os_debug_entry_point;
struct
{
u32 queue_offset;
u16 queue_size;
u8 queue_phy_id;
u8 queue_log_id;
} q_info[SEC2_QUEUE_NUM];
u32 nv_managed_area_offset;
u16 nv_managed_area_size;
};
union nv_flcn_msg_sec2_init {
u8 msg_type;
struct sec2_init_msg_sec2_init sec2_init;
};
#endif /* NVGPU_SEC2_IF_SEC2_H */