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gpu: nvgpu: prof: add new resource type

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Add new profiler resource type NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER.
Introduce regops HAL get_hwpm_pc_sampler_register_ranges to get
allowlist for PC_SAMPLER resources. Re-generate allowlist files to include
register ranges for PC_SAMPLER resources.

Update uapi header to advertise new resource type
NVGPU_PROFILER_PM_RESOURCE_ARG_PC_SAMPLER.

Bug 3408536

Change-Id: I7009ef822665771eed727da48ef1e89dcc6b9c4b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2689057
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Antony Clince Alex
2022-03-29 08:35:06 +00:00
committed by mobile promotions
parent 11819380e8
commit 19a8adeae1
19 changed files with 381 additions and 78 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/gpu/nvgpu/common/profiler/profiler.c
View File

@@ -234,6 +234,11 @@ int nvgpu_profiler_pm_resource_reserve(struct nvgpu_profiler_object *prof,
NVGPU_DBG_REG_OP_TYPE_GLOBAL;
}
if (pm_resource == NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER) {
prof->reg_op_type[NVGPU_HWPM_REGISTER_TYPE_PC_SAMPLER] =
NVGPU_DBG_REG_OP_TYPE_GR_CTX;
}
nvgpu_log(g, gpu_dbg_prof,
"Granted reservation for profiler handle %u, resource %u, scope %u",
prof->prof_handle, pm_resource, prof->scope);
@@ -913,6 +918,11 @@ static u32 get_pm_resource_register_range_map_entry_count(struct nvgpu_profiler_
count += range_count;
}
if (prof->reserved[NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER]) {
g->ops.regops.get_hwpm_pc_sampler_register_ranges(&range_count);
count += range_count;
}
return count;
}
@@ -1013,6 +1023,12 @@ static int nvgpu_profiler_build_regops_allowlist(struct nvgpu_profiler_object *p
NVGPU_HWPM_REGISTER_TYPE_HWPM_PMA_CHANNEL);
}
if (prof->reserved[NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER]) {
range = g->ops.regops.get_hwpm_pc_sampler_register_ranges(&range_count);
add_range_to_map(range, range_count, map, &map_index,
NVGPU_HWPM_REGISTER_TYPE_PC_SAMPLER);
}
add_test_range_to_map(g, map, &map_index, NVGPU_HWPM_REGISTER_TYPE_TEST);
nvgpu_log(g, gpu_dbg_prof, "Allowlist map created successfully for handle %u",

1
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1438,6 +1438,7 @@ static const struct gops_regops ga10b_ops_regops = {
.get_hwpm_perfmon_register_ranges = ga10b_get_hwpm_perfmon_register_ranges,
.get_hwpm_router_register_ranges = ga10b_get_hwpm_router_register_ranges,
.get_hwpm_pma_channel_register_ranges = ga10b_get_hwpm_pma_channel_register_ranges,
.get_hwpm_pc_sampler_register_ranges = ga10b_get_hwpm_pc_sampler_register_ranges,
.get_hwpm_pma_trigger_register_ranges = ga10b_get_hwpm_pma_trigger_register_ranges,
.get_smpc_register_ranges = ga10b_get_smpc_register_ranges,
.get_cau_register_ranges = ga10b_get_cau_register_ranges,

1
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1234,6 +1234,7 @@ static const struct gops_regops gv11b_ops_regops = {
.get_hwpm_router_register_ranges = gv11b_get_hwpm_router_register_ranges,
.get_hwpm_pma_channel_register_ranges = gv11b_get_hwpm_pma_channel_register_ranges,
.get_hwpm_pma_trigger_register_ranges = gv11b_get_hwpm_pma_trigger_register_ranges,
.get_hwpm_pc_sampler_register_ranges = gv11b_get_hwpm_pc_sampler_register_ranges,
.get_smpc_register_ranges = gv11b_get_smpc_register_ranges,
.get_cau_register_ranges = NULL,
.get_hwpm_perfmux_register_ranges = gv11b_get_hwpm_perfmux_register_ranges,

1
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1300,6 +1300,7 @@ static const struct gops_regops tu104_ops_regops = {
.get_hwpm_router_register_ranges = tu104_get_hwpm_router_register_ranges,
.get_hwpm_pma_channel_register_ranges = tu104_get_hwpm_pma_channel_register_ranges,
.get_hwpm_pma_trigger_register_ranges = tu104_get_hwpm_pma_trigger_register_ranges,
.get_hwpm_pc_sampler_register_ranges = tu104_get_hwpm_pc_sampler_register_ranges,
.get_smpc_register_ranges = tu104_get_smpc_register_ranges,
.get_cau_register_ranges = tu104_get_cau_register_ranges,
.get_hwpm_perfmux_register_ranges = tu104_get_hwpm_perfmux_register_ranges,

317
drivers/gpu/nvgpu/hal/regops/allowlist_ga100.c
View File

@@ -380,10 +380,12 @@ static const struct nvgpu_pm_resource_register_range ga100_hwpm_router_register_
};
static const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_channel_register_ranges[] = {
{0x0024a00c, 0x0024a00c},
{0x0024a610, 0x0024a628},
{0x0024a634, 0x0024a658},
{0x0024a730, 0x0024a734},
{0x0024a00c, 0x0024a00c},
{0x0024a75c, 0x0024a75c},
};
static const struct nvgpu_pm_resource_register_range ga100_hwpm_pma_trigger_register_ranges[] = {
@@ -753,486 +755,575 @@ static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register
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{0x0052e1ac, 0x0052e1ac},
{0x0052e1ec, 0x0052e1ec},
{0x0052e2b0, 0x0052e2b0},
{0x0052e304, 0x0052e304},
{0x0052e3dc, 0x0052e3dc},
{0x0052e40c, 0x0052e40c},
{0x0052e664, 0x0052e664},
{0x0052e854, 0x0052e854},
{0x0052e9ac, 0x0052e9ac},
{0x0052e9ec, 0x0052e9ec},
{0x0052eab0, 0x0052eab0},
{0x0052eb04, 0x0052eb04},
{0x0052ebdc, 0x0052ebdc},
{0x0052ec0c, 0x0052ec0c},
{0x0052ee64, 0x0052ee64},
{0x0052f054, 0x0052f054},
{0x0052f1ac, 0x0052f1ac},
{0x0052f1ec, 0x0052f1ec},
{0x0052f2b0, 0x0052f2b0},
{0x0052f304, 0x0052f304},
{0x0052f3dc, 0x0052f3dc},
{0x0052f40c, 0x0052f40c},
{0x0052f664, 0x0052f664},
{0x0052f854, 0x0052f854},
{0x0052f9ac, 0x0052f9ac},
{0x0052f9ec, 0x0052f9ec},
{0x0052fab0, 0x0052fab0},
{0x0052fb04, 0x0052fb04},
{0x0052fbdc, 0x0052fbdc},
{0x0052fc0c, 0x0052fc0c},
{0x0052fe64, 0x0052fe64},
{0x00534054, 0x00534054},
{0x005341ac, 0x005341ac},
{0x005341ec, 0x005341ec},
{0x005342b0, 0x005342b0},
{0x00534304, 0x00534304},
{0x005343dc, 0x005343dc},
{0x0053440c, 0x0053440c},
{0x00534664, 0x00534664},
{0x00534854, 0x00534854},
{0x005349ac, 0x005349ac},
{0x005349ec, 0x005349ec},
{0x00534ab0, 0x00534ab0},
{0x00534b04, 0x00534b04},
{0x00534bdc, 0x00534bdc},
{0x00534c0c, 0x00534c0c},
{0x00534e64, 0x00534e64},
{0x00535054, 0x00535054},
{0x005351ac, 0x005351ac},
{0x005351ec, 0x005351ec},
{0x005352b0, 0x005352b0},
{0x00535304, 0x00535304},
{0x005353dc, 0x005353dc},
{0x0053540c, 0x0053540c},
{0x00535664, 0x00535664},
{0x00535854, 0x00535854},
{0x005359ac, 0x005359ac},
{0x005359ec, 0x005359ec},
{0x00535ab0, 0x00535ab0},
{0x00535b04, 0x00535b04},
{0x00535bdc, 0x00535bdc},
{0x00535c0c, 0x00535c0c},
{0x00535e64, 0x00535e64},
{0x00536054, 0x00536054},
{0x005361ac, 0x005361ac},
{0x005361ec, 0x005361ec},
{0x005362b0, 0x005362b0},
{0x00536304, 0x00536304},
{0x005363dc, 0x005363dc},
{0x0053640c, 0x0053640c},
{0x00536664, 0x00536664},
{0x00536854, 0x00536854},
{0x005369ac, 0x005369ac},
{0x005369ec, 0x005369ec},
{0x00536ab0, 0x00536ab0},
{0x00536b04, 0x00536b04},
{0x00536bdc, 0x00536bdc},
{0x00536c0c, 0x00536c0c},
{0x00536e64, 0x00536e64},
{0x00537054, 0x00537054},
{0x005371ac, 0x005371ac},
{0x005371ec, 0x005371ec},
{0x005372b0, 0x005372b0},
{0x00537304, 0x00537304},
{0x005373dc, 0x005373dc},
{0x0053740c, 0x0053740c},
{0x00537664, 0x00537664},
{0x00537854, 0x00537854},
{0x005379ac, 0x005379ac},
{0x005379ec, 0x005379ec},
{0x00537ab0, 0x00537ab0},
{0x00537b04, 0x00537b04},
{0x00537bdc, 0x00537bdc},
{0x00537c0c, 0x00537c0c},
{0x00537e64, 0x00537e64},
{0x0053c054, 0x0053c054},
{0x0053c1ac, 0x0053c1ac},
{0x0053c1ec, 0x0053c1ec},
{0x0053c2b0, 0x0053c2b0},
{0x0053c304, 0x0053c304},
{0x0053c3dc, 0x0053c3dc},
{0x0053c40c, 0x0053c40c},
{0x0053c664, 0x0053c664},
{0x0053c854, 0x0053c854},
{0x0053c9ac, 0x0053c9ac},
{0x0053c9ec, 0x0053c9ec},
{0x0053cab0, 0x0053cab0},
{0x0053cb04, 0x0053cb04},
{0x0053cbdc, 0x0053cbdc},
{0x0053cc0c, 0x0053cc0c},
{0x0053ce64, 0x0053ce64},
{0x0053d054, 0x0053d054},
{0x0053d1ac, 0x0053d1ac},
{0x0053d1ec, 0x0053d1ec},
{0x0053d2b0, 0x0053d2b0},
{0x0053d304, 0x0053d304},
{0x0053d3dc, 0x0053d3dc},
{0x0053d40c, 0x0053d40c},
{0x0053d664, 0x0053d664},
{0x0053d854, 0x0053d854},
{0x0053d9ac, 0x0053d9ac},
{0x0053d9ec, 0x0053d9ec},
{0x0053dab0, 0x0053dab0},
{0x0053db04, 0x0053db04},
{0x0053dbdc, 0x0053dbdc},
{0x0053dc0c, 0x0053dc0c},
{0x0053de64, 0x0053de64},
{0x0053e054, 0x0053e054},
{0x0053e1ac, 0x0053e1ac},
{0x0053e1ec, 0x0053e1ec},
{0x0053e2b0, 0x0053e2b0},
{0x0053e304, 0x0053e304},
{0x0053e3dc, 0x0053e3dc},
{0x0053e40c, 0x0053e40c},
{0x0053e664, 0x0053e664},
{0x0053e854, 0x0053e854},
{0x0053e9ac, 0x0053e9ac},
{0x0053e9ec, 0x0053e9ec},
{0x0053eab0, 0x0053eab0},
{0x0053eb04, 0x0053eb04},
{0x0053ebdc, 0x0053ebdc},
{0x0053ec0c, 0x0053ec0c},
{0x0053ee64, 0x0053ee64},
{0x0053f054, 0x0053f054},
{0x0053f1ac, 0x0053f1ac},
{0x0053f1ec, 0x0053f1ec},
{0x0053f2b0, 0x0053f2b0},
{0x0053f304, 0x0053f304},
{0x0053f3dc, 0x0053f3dc},
{0x0053f40c, 0x0053f40c},
{0x0053f664, 0x0053f664},
{0x0053f854, 0x0053f854},
{0x0053f9ac, 0x0053f9ac},
{0x0053f9ec, 0x0053f9ec},
{0x0053fab0, 0x0053fab0},
{0x0053fb04, 0x0053fb04},
{0x0053fbdc, 0x0053fbdc},
{0x0053fc0c, 0x0053fc0c},
{0x0053fe64, 0x0053fe64},
{0x00419854, 0x00419854},
{0x004199ac, 0x004199ac},
{0x004199ec, 0x004199ec},
{0x00419ab0, 0x00419ab0},
{0x00419b04, 0x00419b04},
{0x00419bdc, 0x00419bdc},
{0x00419c0c, 0x00419c0c},
{0x00419e64, 0x00419e64},
{0x0041c054, 0x0041c054},
{0x0041c1ac, 0x0041c1ac},
{0x0041c1ec, 0x0041c1ec},
{0x0041c2b0, 0x0041c2b0},
{0x0041c304, 0x0041c304},
{0x0041c3dc, 0x0041c3dc},
{0x0041c40c, 0x0041c40c},
{0x0041c664, 0x0041c664},
{0x0041c854, 0x0041c854},
{0x0041c9ac, 0x0041c9ac},
{0x0041c9ec, 0x0041c9ec},
{0x0041cab0, 0x0041cab0},
{0x0041cb04, 0x0041cb04},
{0x0041cbdc, 0x0041cbdc},
{0x0041cc0c, 0x0041cc0c},
{0x0041ce64, 0x0041ce64},
{0x0041d054, 0x0041d054},
{0x0041d1ac, 0x0041d1ac},
{0x0041d1ec, 0x0041d1ec},
{0x0041d2b0, 0x0041d2b0},
{0x0041d304, 0x0041d304},
{0x0041d3dc, 0x0041d3dc},
{0x0041d40c, 0x0041d40c},
{0x0041d664, 0x0041d664},
{0x0041d854, 0x0041d854},
{0x0041d9ac, 0x0041d9ac},
{0x0041d9ec, 0x0041d9ec},
{0x0041dab0, 0x0041dab0},
{0x0041db04, 0x0041db04},
{0x0041dbdc, 0x0041dbdc},
{0x0041dc0c, 0x0041dc0c},
{0x0041de64, 0x0041de64},
{0x0041e054, 0x0041e054},
{0x0041e1ac, 0x0041e1ac},
{0x0041e1ec, 0x0041e1ec},
{0x0041e2b0, 0x0041e2b0},
{0x0041e304, 0x0041e304},
{0x0041e3dc, 0x0041e3dc},
{0x0041e40c, 0x0041e40c},
{0x0041e664, 0x0041e664},
{0x0041e854, 0x0041e854},
{0x0041e9ac, 0x0041e9ac},
{0x0041e9ec, 0x0041e9ec},
{0x0041eab0, 0x0041eab0},
{0x0041eb04, 0x0041eb04},
{0x0041ebdc, 0x0041ebdc},
{0x0041ec0c, 0x0041ec0c},
{0x0041ee64, 0x0041ee64},
{0x0041f054, 0x0041f054},
{0x0041f1ac, 0x0041f1ac},
{0x0041f1ec, 0x0041f1ec},
{0x0041f2b0, 0x0041f2b0},
{0x0041f304, 0x0041f304},
{0x0041f3dc, 0x0041f3dc},
{0x0041f40c, 0x0041f40c},
{0x0041f664, 0x0041f664},
{0x0041f854, 0x0041f854},
{0x0041f9ac, 0x0041f9ac},
{0x0041f9ec, 0x0041f9ec},
{0x0041fab0, 0x0041fab0},
{0x0041fb04, 0x0041fb04},
{0x0041fbdc, 0x0041fbdc},
{0x0041fc0c, 0x0041fc0c},
{0x0041fe64, 0x0041fe64},
{0x00501854, 0x00501854},
{0x005019ac, 0x005019ac},
{0x005019ec, 0x005019ec},
{0x00501ab0, 0x00501ab0},
{0x00501b04, 0x00501b04},
{0x00501bdc, 0x00501bdc},
{0x00501c0c, 0x00501c0c},
{0x00501e64, 0x00501e64},
{0x00509854, 0x00509854},
{0x005099ac, 0x005099ac},
{0x005099ec, 0x005099ec},
{0x00509ab0, 0x00509ab0},
{0x00509b04, 0x00509b04},
{0x00509bdc, 0x00509bdc},
{0x00509c0c, 0x00509c0c},
{0x00509e64, 0x00509e64},
{0x00511854, 0x00511854},
{0x005119ac, 0x005119ac},
{0x005119ec, 0x005119ec},
{0x00511ab0, 0x00511ab0},
{0x00511b04, 0x00511b04},
{0x00511bdc, 0x00511bdc},
{0x00511c0c, 0x00511c0c},
{0x00511e64, 0x00511e64},
{0x00519854, 0x00519854},
{0x005199ac, 0x005199ac},
{0x005199ec, 0x005199ec},
{0x00519ab0, 0x00519ab0},
{0x00519b04, 0x00519b04},
{0x00519bdc, 0x00519bdc},
{0x00519c0c, 0x00519c0c},
{0x00519e64, 0x00519e64},
{0x00521854, 0x00521854},
{0x005219ac, 0x005219ac},
{0x005219ec, 0x005219ec},
{0x00521ab0, 0x00521ab0},
{0x00521b04, 0x00521b04},
{0x00521bdc, 0x00521bdc},
{0x00521c0c, 0x00521c0c},
{0x00521e64, 0x00521e64},
{0x00529854, 0x00529854},
{0x005299ac, 0x005299ac},
{0x005299ec, 0x005299ec},
{0x00529ab0, 0x00529ab0},
{0x00529b04, 0x00529b04},
{0x00529bdc, 0x00529bdc},
{0x00529c0c, 0x00529c0c},
{0x00529e64, 0x00529e64},
{0x00531854, 0x00531854},
{0x005319ac, 0x005319ac},
{0x005319ec, 0x005319ec},
{0x00531ab0, 0x00531ab0},
{0x00531b04, 0x00531b04},
{0x00531bdc, 0x00531bdc},
{0x00531c0c, 0x00531c0c},
{0x00531e64, 0x00531e64},
{0x00539854, 0x00539854},
{0x005399ac, 0x005399ac},
{0x005399ec, 0x005399ec},
{0x00539ab0, 0x00539ab0},
{0x00539b04, 0x00539b04},
{0x00539bdc, 0x00539bdc},
@@ -1359,12 +1450,14 @@ static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register
{0x00006000, 0x00006000},
{0x00006400, 0x00006400},
{0x00006800, 0x00006800},
{0x0000a084, 0x0000a084},
{0x0000cc98, 0x0000cc98},
{0x000884e0, 0x000884e0},
{0x000884f4, 0x000884f4},
{0x0008e00c, 0x0008e00c},
{0x00100c18, 0x00100c20},
{0x00100c84, 0x00100c84},
{0x00104030, 0x00104030},
{0x00105068, 0x00105068},
{0x00105128, 0x00105128},
{0x001051e8, 0x001051e8},
@@ -1385,6 +1478,8 @@ static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register
{0x00105d28, 0x00105d28},
{0x0010a0a8, 0x0010a0a8},
{0x0010a4f0, 0x0010a4f0},
{0x00122228, 0x00122228},
{0x00124228, 0x00124228},
{0x0013cc14, 0x0013cc14},
{0x0013cc24, 0x0013cc28},
{0x0013cc54, 0x0013cc54},
@@ -1427,6 +1522,74 @@ static const struct nvgpu_pm_resource_register_range ga100_hwpm_perfmux_register
{0x0013cb94, 0x0013cb94},
};
static const struct nvgpu_pm_resource_register_range ga100_hwpm_pc_sampler_register_ranges[] = {
{0x005043dc, 0x005043dc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x00509bdc, 0x00509bdc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x00509bdc, 0x00509bdc},
{0x0050a3dc, 0x0050a3dc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x00509bdc, 0x00509bdc},
{0x0050a3dc, 0x0050a3dc},
{0x0050abdc, 0x0050abdc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x00509bdc, 0x00509bdc},
{0x0050a3dc, 0x0050a3dc},
{0x0050abdc, 0x0050abdc},
{0x0050b3dc, 0x0050b3dc},
{0x00419bdc, 0x00419bdc},
};
static const struct nvgpu_pm_resource_register_range ga100_cau_register_ranges[] = {
{0x00504180, 0x005041b4},
{0x005041c0, 0x005041f4},
@@ -1712,6 +1875,14 @@ const struct nvgpu_pm_resource_register_range
return ga100_hwpm_perfmux_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*ga100_get_hwpm_pc_sampler_register_ranges(u32 *count)
{
*count = (u32)(sizeof(ga100_hwpm_pc_sampler_register_ranges) /
sizeof(ga100_hwpm_pc_sampler_register_ranges[0]));
return ga100_hwpm_pc_sampler_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*ga100_get_cau_register_ranges(u32 *count)
{

4
drivers/gpu/nvgpu/hal/regops/allowlist_ga100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -55,6 +55,8 @@ const struct nvgpu_pm_resource_register_range
*ga100_get_smpc_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga100_get_hwpm_perfmux_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga100_get_hwpm_pc_sampler_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga100_get_cau_register_ranges(u32 *count);

20
drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.c
View File

@@ -652,6 +652,18 @@ static const struct nvgpu_pm_resource_register_range ga10b_hwpm_perfmux_register
{0x0013cb94, 0x0013cb94},
};
static const struct nvgpu_pm_resource_register_range ga10b_hwpm_pc_sampler_register_ranges[] = {
{0x005043dc, 0x005043dc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00419bdc, 0x00419bdc},
};
static const struct nvgpu_pm_resource_register_range ga10b_cau_register_ranges[] = {
{0x00504180, 0x005041ac},
{0x005041b4, 0x005041e8},
@@ -820,6 +832,14 @@ const struct nvgpu_pm_resource_register_range
return ga10b_hwpm_perfmux_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*ga10b_get_hwpm_pc_sampler_register_ranges(u32 *count)
{
*count = (u32)(sizeof(ga10b_hwpm_pc_sampler_register_ranges) /
sizeof(ga10b_hwpm_pc_sampler_register_ranges[0]));
return ga10b_hwpm_pc_sampler_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*ga10b_get_cau_register_ranges(u32 *count)
{

2
drivers/gpu/nvgpu/hal/regops/allowlist_ga10b.h
View File

@@ -55,6 +55,8 @@ const struct nvgpu_pm_resource_register_range
*ga10b_get_smpc_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga10b_get_hwpm_perfmux_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga10b_get_hwpm_pc_sampler_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*ga10b_get_cau_register_ranges(u32 *count);

16
drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.c
View File

@@ -496,6 +496,14 @@ static const struct nvgpu_pm_resource_register_range gv11b_hwpm_perfmux_register
{0x00900100, 0x00900100},
};
static const struct nvgpu_pm_resource_register_range gv11b_hwpm_pc_sampler_register_ranges[] = {
{0x005043dc, 0x005043dc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x00419bdc, 0x00419bdc},
};
u32 gv11b_get_hwpm_perfmon_register_stride(void)
{
return 0x00000200;
@@ -604,3 +612,11 @@ const struct nvgpu_pm_resource_register_range
return gv11b_hwpm_perfmux_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*gv11b_get_hwpm_pc_sampler_register_ranges(u32 *count)
{
*count = (u32)(sizeof(gv11b_hwpm_pc_sampler_register_ranges) /
sizeof(gv11b_hwpm_pc_sampler_register_ranges[0]));
return gv11b_hwpm_pc_sampler_register_ranges;
}

4
drivers/gpu/nvgpu/hal/regops/allowlist_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -53,5 +53,7 @@ const struct nvgpu_pm_resource_register_range
*gv11b_get_smpc_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*gv11b_get_hwpm_perfmux_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*gv11b_get_hwpm_pc_sampler_register_ranges(u32 *count);
#endif /* NVGPU_GV11B_REGOPS_ALLOWLIST_H */

48
drivers/gpu/nvgpu/hal/regops/allowlist_tu104.c
View File

@@ -1117,6 +1117,46 @@ static const struct nvgpu_pm_resource_register_range tu104_hwpm_perfmux_register
{0x00a1ec70, 0x00a1ec74},
};
static const struct nvgpu_pm_resource_register_range tu104_hwpm_pc_sampler_register_ranges[] = {
{0x005043dc, 0x005043dc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x00504bdc, 0x00504bdc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x005053dc, 0x005053dc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x00505bdc, 0x00505bdc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x005063dc, 0x005063dc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x00506bdc, 0x00506bdc},
{0x005073dc, 0x005073dc},
{0x00507bdc, 0x00507bdc},
{0x005083dc, 0x005083dc},
{0x00508bdc, 0x00508bdc},
{0x005093dc, 0x005093dc},
{0x00419bdc, 0x00419bdc},
};
static const struct nvgpu_pm_resource_register_range tu104_cau_register_ranges[] = {
{0x00419980, 0x004199b4},
{0x004199c0, 0x004199f4},
@@ -1338,6 +1378,14 @@ const struct nvgpu_pm_resource_register_range
return tu104_hwpm_perfmux_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*tu104_get_hwpm_pc_sampler_register_ranges(u32 *count)
{
*count = (u32)(sizeof(tu104_hwpm_pc_sampler_register_ranges) /
sizeof(tu104_hwpm_pc_sampler_register_ranges[0]));
return tu104_hwpm_pc_sampler_register_ranges;
}
const struct nvgpu_pm_resource_register_range
*tu104_get_cau_register_ranges(u32 *count)
{

4
drivers/gpu/nvgpu/hal/regops/allowlist_tu104.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -55,6 +55,8 @@ const struct nvgpu_pm_resource_register_range
*tu104_get_smpc_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*tu104_get_hwpm_perfmux_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*tu104_get_hwpm_pc_sampler_register_ranges(u32 *count);
const struct nvgpu_pm_resource_register_range
*tu104_get_cau_register_ranges(u32 *count);

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_ga10b.c
View File

@@ -902,6 +902,7 @@ static const struct gops_regops vgpu_ga10b_ops_regops = {
.get_hwpm_perfmon_register_ranges = ga10b_get_hwpm_perfmon_register_ranges,
.get_hwpm_router_register_ranges = ga10b_get_hwpm_router_register_ranges,
.get_hwpm_pma_channel_register_ranges = ga10b_get_hwpm_pma_channel_register_ranges,
.get_hwpm_pc_sampler_register_ranges = ga10b_get_hwpm_pc_sampler_register_ranges,
.get_hwpm_pma_trigger_register_ranges = ga10b_get_hwpm_pma_trigger_register_ranges,
.get_smpc_register_ranges = ga10b_get_smpc_register_ranges,
.get_cau_register_ranges = ga10b_get_cau_register_ranges,

1
drivers/gpu/nvgpu/hal/vgpu/init/vgpu_hal_gv11b.c
View File

@@ -874,6 +874,7 @@ static const struct gops_regops vgpu_gv11b_ops_regops = {
.get_hwpm_pma_channel_register_ranges = gv11b_get_hwpm_pma_channel_register_ranges,
.get_hwpm_pma_trigger_register_ranges = gv11b_get_hwpm_pma_trigger_register_ranges,
.get_smpc_register_ranges = gv11b_get_smpc_register_ranges,
.get_hwpm_pc_sampler_register_ranges = gv11b_get_hwpm_pc_sampler_register_ranges,
.get_cau_register_ranges = NULL,
.get_hwpm_perfmux_register_ranges = gv11b_get_hwpm_perfmux_register_ranges,
};

2
drivers/gpu/nvgpu/include/nvgpu/gops/debugger.h
View File

@@ -57,6 +57,8 @@ struct gops_regops {
(*get_hwpm_router_register_ranges)(u32 *count);
const struct nvgpu_pm_resource_register_range *
(*get_hwpm_pma_channel_register_ranges)(u32 *count);
const struct nvgpu_pm_resource_register_range *
(*get_hwpm_pc_sampler_register_ranges)(u32 *count);
const struct nvgpu_pm_resource_register_range *
(*get_hwpm_pma_trigger_register_ranges)(u32 *count);
const struct nvgpu_pm_resource_register_range *

3
drivers/gpu/nvgpu/include/nvgpu/pm_reservation.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,6 +39,7 @@ enum nvgpu_profiler_pm_resource_type {
NVGPU_PROFILER_PM_RESOURCE_TYPE_HWPM_LEGACY,
NVGPU_PROFILER_PM_RESOURCE_TYPE_SMPC,
NVGPU_PROFILER_PM_RESOURCE_TYPE_PMA_STREAM,
NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER,
NVGPU_PROFILER_PM_RESOURCE_TYPE_COUNT,
};

3
drivers/gpu/nvgpu/include/nvgpu/regops_allowlist.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,7 @@ enum nvgpu_pm_resource_hwpm_register_type {
NVGPU_HWPM_REGISTER_TYPE_SMPC,
NVGPU_HWPM_REGISTER_TYPE_CAU,
NVGPU_HWPM_REGISTER_TYPE_HWPM_PMA_CHANNEL,
NVGPU_HWPM_REGISTER_TYPE_PC_SAMPLER,
NVGPU_HWPM_REGISTER_TYPE_TEST,
NVGPU_HWPM_REGISTER_TYPE_COUNT,
};

14
drivers/gpu/nvgpu/os/linux/ioctl_prof.c
View File

@@ -267,6 +267,9 @@ static int nvgpu_prof_ioctl_get_pm_resource_type(u32 resource,
case NVGPU_PROFILER_PM_RESOURCE_ARG_SMPC:
*pm_resource = NVGPU_PROFILER_PM_RESOURCE_TYPE_SMPC;
return 0;
case NVGPU_PROFILER_PM_RESOURCE_ARG_PC_SAMPLER:
*pm_resource = NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER;
return 0;
default:
break;
}
@@ -307,6 +310,17 @@ static int nvgpu_prof_ioctl_reserve_pm_resource(struct nvgpu_profiler_object *pr
nvgpu_err(g, "SMPC global mode not supported");
return -EINVAL;
}
/*
* PC_SAMPLER resources are always context switched with a GR
* context, so reservation scope is always context. This
* requires that profiler object is instantiated with a valid
* GR context.
*/
if ((pm_resource == NVGPU_PROFILER_PM_RESOURCE_TYPE_PC_SAMPLER)
&& (prof->tsg == NULL)) {
nvgpu_err(g, "PC_SAMPLER reservation is only allowed wth context bound");
return -EINVAL;
}
if (flag_ctxsw) {
prof->ctxsw[pm_resource] = true;
} else {

1
include/uapi/linux/nvgpu.h
View File

@@ -621,6 +621,7 @@ struct nvgpu_profiler_bind_context_args {
#define NVGPU_PROFILER_PM_RESOURCE_ARG_HWPM_LEGACY 0U
#define NVGPU_PROFILER_PM_RESOURCE_ARG_SMPC 1U
#define NVGPU_PROFILER_PM_RESOURCE_ARG_PC_SAMPLER 2U
struct nvgpu_profiler_reserve_pm_resource_args {
__u32 resource; /* in: NVGPU_PROFILER_PM_RESOURCE_ARG_* resource to be reserved */