gpu: nvgpu: vgpu: create vgpu intr unit

Move interrupt related functions to intr/intr_vgpu.c
creating new vgpu unit intr.

Jira GVSCI-334

Change-Id: I6473b9b932cef34c30a02b42228cbeb9e0dea195
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2082184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -492,6 +492,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	common/vgpu/mm/vm_vgpu.o \
 	common/vgpu/vgpu.o \
 	common/vgpu/ivc/comm_vgpu.o \
+	common/vgpu/intr/intr_vgpu.o \
 	common/vgpu/ptimer/ptimer_vgpu.o \
 	common/vgpu/debugger_vgpu.o \
 	common/vgpu/tsg_vgpu.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -406,6 +406,7 @@ endif
 ifeq ($(IGPU_VIRT_SUPPORT), 1)
 srcs += common/vgpu/vgpu.c \
 	common/vgpu/ivc/comm_vgpu.c \
+	common/vgpu/intr/intr_vgpu.c \
 	common/vgpu/ptimer/ptimer_vgpu.c \
 	common/vgpu/fifo/fifo_vgpu.c \
 	common/vgpu/fifo/runlist_vgpu.c \

drivers/gpu/nvgpu/common/vgpu/fifo/fifo_vgpu.h

@@ -29,6 +29,7 @@ struct gk20a;
 struct channel_gk20a;
 struct fifo_gk20a;
 struct tsg_gk20a;
+struct tegra_vgpu_fifo_intr_info;
 
 int vgpu_fifo_setup_sw(struct gk20a *g);
 void vgpu_fifo_cleanup_sw(struct gk20a *g);
@@ -56,4 +57,6 @@ int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
 void vgpu_tsg_enable(struct tsg_gk20a *tsg);
 int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask);
 void vgpu_channel_free_ctx_header(struct channel_gk20a *c);
+int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
+
 #endif /* NVGPU_FIFO_VGPU_H */

drivers/gpu/nvgpu/common/vgpu/gr/gr_vgpu.h

@@ -37,6 +37,8 @@ struct tsg_gk20a;
 struct vm_gk20a;
 struct nvgpu_gr_ctx;
 struct nvgpu_gr_zcull;
+struct tegra_vgpu_gr_intr_info;
+struct tegra_vgpu_sm_esr_info;
 
 void vgpu_gr_detect_sm_arch(struct gk20a *g);
 int vgpu_gr_init_ctx_state(struct gk20a *g);
@@ -83,5 +85,8 @@ void vgpu_gr_init_cyclestats(struct gk20a *g);
 int vgpu_gr_set_preemption_mode(struct channel_gk20a *ch,
 				u32 graphics_preempt_mode,
 				u32 compute_preempt_mode);
+int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
+void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
+			struct tegra_vgpu_sm_esr_info *info);
 
 #endif /* NVGPU_GR_VGPU_H */

drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/vgpu/vgpu.h>
+#include <nvgpu/gk20a.h>
+
+#include <nvgpu/vgpu/vgpu_ivc.h>
+
+#include "intr_vgpu.h"
+#include "common/vgpu/gr/fecs_trace_vgpu.h"
+#include "common/vgpu/fifo/fifo_vgpu.h"
+#include "common/vgpu/mm/mm_vgpu.h"
+#include "common/vgpu/gr/gr_vgpu.h"
+
+int vgpu_intr_thread(void *dev_id)
+{
+	struct gk20a *g = dev_id;
+	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
+
+	while (true) {
+		struct tegra_vgpu_intr_msg *msg;
+		u32 sender;
+		void *handle;
+		size_t size;
+		int err;
+
+		err = vgpu_ivc_recv(TEGRA_VGPU_QUEUE_INTR, &handle,
+					(void **)&msg, &size, &sender);
+		if (err == -ETIME) {
+			continue;
+		}
+		if (err != 0) {
+			nvgpu_do_assert_print(g,
+				"Unexpected vgpu_ivc_recv err=%d", err);
+			continue;
+		}
+
+		if (msg->event == TEGRA_VGPU_EVENT_ABORT) {
+			vgpu_ivc_release(handle);
+			break;
+		}
+
+		switch (msg->event) {
+		case TEGRA_VGPU_EVENT_INTR:
+			if (msg->unit == TEGRA_VGPU_INTR_GR) {
+				vgpu_gr_isr(g, &msg->info.gr_intr);
+			} else if (msg->unit == TEGRA_VGPU_INTR_FIFO) {
+				vgpu_fifo_isr(g, &msg->info.fifo_intr);
+			}
+			break;
+#ifdef CONFIG_GK20A_CTXSW_TRACE
+		case TEGRA_VGPU_EVENT_FECS_TRACE:
+			vgpu_fecs_trace_data_update(g);
+			break;
+#endif
+		case TEGRA_VGPU_EVENT_CHANNEL:
+			vgpu_handle_channel_event(g, &msg->info.channel_event);
+			break;
+		case TEGRA_VGPU_EVENT_SM_ESR:
+			vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr);
+			break;
+		case TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP:
+			g->ops.semaphore_wakeup(g,
+					!!msg->info.sem_wakeup.post_events);
+			break;
+		case TEGRA_VGPU_EVENT_CHANNEL_CLEANUP:
+			vgpu_channel_abort_cleanup(g,
+					msg->info.ch_cleanup.chid);
+			break;
+		case TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER:
+			vgpu_set_error_notifier(g,
+						&msg->info.set_error_notifier);
+			break;
+		default:
+			nvgpu_err(g, "unknown event %u", msg->event);
+			break;
+		}
+
+		vgpu_ivc_release(handle);
+	}
+
+	while (!nvgpu_thread_should_stop(&priv->intr_handler)) {
+		nvgpu_msleep(10);
+	}
+	return 0;
+}

drivers/gpu/nvgpu/common/vgpu/intr/intr_vgpu.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef INTR_VGPU_H
+#define INTR_VGPU_H
+
+int vgpu_intr_thread(void *dev_id);
+
+#endif

drivers/gpu/nvgpu/common/vgpu/vgpu.c

@@ -117,79 +117,6 @@ static void vgpu_set_error_notifier(struct gk20a *g,
 	g->ops.fifo.set_error_notifier(ch, p->error);
 }
 
-int vgpu_intr_thread(void *dev_id)
-{
-	struct gk20a *g = dev_id;
-	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
-
-	while (true) {
-		struct tegra_vgpu_intr_msg *msg;
-		u32 sender;
-		void *handle;
-		size_t size;
-		int err;
-
-		err = vgpu_ivc_recv(TEGRA_VGPU_QUEUE_INTR, &handle,
-					(void **)&msg, &size, &sender);
-		if (err == -ETIME) {
-			continue;
-		}
-		if (err != 0) {
-			nvgpu_do_assert_print(g,
-				"Unexpected vgpu_ivc_recv err=%d", err);
-			continue;
-		}
-
-		if (msg->event == TEGRA_VGPU_EVENT_ABORT) {
-			vgpu_ivc_release(handle);
-			break;
-		}
-
-		switch (msg->event) {
-		case TEGRA_VGPU_EVENT_INTR:
-			if (msg->unit == TEGRA_VGPU_INTR_GR) {
-				vgpu_gr_isr(g, &msg->info.gr_intr);
-			} else if (msg->unit == TEGRA_VGPU_INTR_FIFO) {
-				vgpu_fifo_isr(g, &msg->info.fifo_intr);
-			}
-			break;
-#ifdef CONFIG_GK20A_CTXSW_TRACE
-		case TEGRA_VGPU_EVENT_FECS_TRACE:
-			vgpu_fecs_trace_data_update(g);
-			break;
-#endif
-		case TEGRA_VGPU_EVENT_CHANNEL:
-			vgpu_handle_channel_event(g, &msg->info.channel_event);
-			break;
-		case TEGRA_VGPU_EVENT_SM_ESR:
-			vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr);
-			break;
-		case TEGRA_VGPU_EVENT_SEMAPHORE_WAKEUP:
-			g->ops.semaphore_wakeup(g,
-					!!msg->info.sem_wakeup.post_events);
-			break;
-		case TEGRA_VGPU_EVENT_CHANNEL_CLEANUP:
-			vgpu_channel_abort_cleanup(g,
-					msg->info.ch_cleanup.chid);
-			break;
-		case TEGRA_VGPU_EVENT_SET_ERROR_NOTIFIER:
-			vgpu_set_error_notifier(g,
-						&msg->info.set_error_notifier);
-			break;
-		default:
-			nvgpu_err(g, "unknown event %u", msg->event);
-			break;
-		}
-
-		vgpu_ivc_release(handle);
-	}
-
-	while (!nvgpu_thread_should_stop(&priv->intr_handler)) {
-		nvgpu_msleep(10);
-	}
-	return 0;
-}
-
 void vgpu_remove_support_common(struct gk20a *g)
 {
 	struct vgpu_priv_data *priv = vgpu_get_priv_data(g);

drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h

@@ -30,8 +30,6 @@
 #include <nvgpu/vgpu/tegra_vgpu.h>
 
 struct device;
-struct tegra_vgpu_gr_intr_info;
-struct tegra_vgpu_fifo_intr_info;
 struct nvgpu_mem;
 struct gk20a;
 struct vm_gk20a;
@@ -64,7 +62,6 @@ static inline u64 vgpu_get_handle(struct gk20a *g)
 }
 
 int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
-int vgpu_intr_thread(void *dev_id);
 void vgpu_remove_support_common(struct gk20a *g);
 void vgpu_detect_chip(struct gk20a *g);
 void vgpu_init_gpu_characteristics(struct gk20a *g);
@@ -72,10 +69,6 @@ int vgpu_init_hal(struct gk20a *g);
 int vgpu_init_hal_os(struct gk20a *g);
 int vgpu_get_constants(struct gk20a *g);
 u64 vgpu_mm_bar1_map_userd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset);
-int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
-void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
-			struct tegra_vgpu_sm_esr_info *info);
-int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
 
 int vgpu_init_mm_support(struct gk20a *g);
 int vgpu_init_gr_support(struct gk20a *g);

drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c

@@ -39,6 +39,7 @@
 #include "common/vgpu/gr/fecs_trace_vgpu.h"
 #include "common/vgpu/clk_vgpu.h"
 #include "common/vgpu/ivc/comm_vgpu.h"
+#include "common/vgpu/intr/intr_vgpu.h"
 #include "gm20b/hal_gm20b.h"
 
 #include "os/linux/module.h"