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gpu: nvgpu: add resume_single_sm gr ops

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This is required to support multiple SM and t19x
sm register address changes

JIRA GPUT19X-75

Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-07-02 16:43:31 -07:00
committed by mobile promotions
parent 29b688960f
commit 1ab0eec6ea
5 changed files with 9 additions and 8 deletions
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8
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -8088,13 +8088,11 @@ void gk20a_gr_suspend_all_sms(struct gk20a *g,
}
}
void gk20a_resume_single_sm(struct gk20a *g,
u32 gpc, u32 tpc)
void gk20a_gr_resume_single_sm(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm)
{
u32 dbgr_control0;
u32 offset;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
/*
* The following requires some clarification. Despite the fact that both
* RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their
@@ -8108,7 +8106,7 @@ void gk20a_resume_single_sm(struct gk20a *g,
* effect, before enabling the run trigger.
*/
offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
/*De-assert stop trigger */
dbgr_control0 =