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gpu: nvgpu: add suspend_all_sms gr ops

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This is required to support multiple SM and t19x
sm register address changes

JIRA GPUT19X-75

Change-Id: Icdae3b6ed67a3d3deeb17f29528184b2d7a70af5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512215
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-07-02 15:39:27 -07:00
committed by mobile promotions
parent 0e2e3898f7
commit 29b688960f
5 changed files with 13 additions and 7 deletions
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2
drivers/gpu/nvgpu/gk20a/gk20a.h
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@@ -373,6 +373,8 @@ struct gpu_ops {
void (*suspend_single_sm)(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm,
u32 global_esr_mask, bool check_errors);
void (*suspend_all_sms)(struct gk20a *g,
u32 global_esr_mask, bool check_errors);
} gr;
struct {
void (*init_hw)(struct gk20a *g);

10
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -1147,7 +1147,7 @@ void gr_gk20a_init_sm_id_table(struct gk20a *g)
* Return number of TPCs in a GPC
* Return 0 if GPC index is invalid i.e. GPC is disabled
*/
static u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index)
u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index)
{
if (gpc_index >= gr->gpc_count)
return 0;
@@ -8047,7 +8047,7 @@ void gk20a_gr_suspend_single_sm(struct gk20a *g,
}
}
void gk20a_suspend_all_sms(struct gk20a *g,
void gk20a_gr_suspend_all_sms(struct gk20a *g,
u32 global_esr_mask, bool check_errors)
{
struct gr_gk20a *gr = &g->gr;
@@ -8062,8 +8062,10 @@ void gk20a_suspend_all_sms(struct gk20a *g,
return;
}
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "suspending all sms");
/* assert stop trigger. uniformity assumption: all SMs will have
* the same state in dbg_control0. */
* the same state in dbg_control0.
*/
dbgr_control0 =
gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r());
dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f();
@@ -8221,7 +8223,7 @@ bool gr_gk20a_suspend_context(struct channel_gk20a *ch)
bool ctx_resident = false;
if (gk20a_is_channel_ctx_resident(ch)) {
gk20a_suspend_all_sms(g, 0, false);
g->ops.gr.suspend_all_sms(g, 0, false);
ctx_resident = true;
} else {
gk20a_disable_channel_tsg(g, ch);

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -618,8 +618,9 @@ void gk20a_resume_all_sms(struct gk20a *g);
void gk20a_gr_suspend_single_sm(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm,
u32 global_esr_mask, bool check_errors);
void gk20a_suspend_all_sms(struct gk20a *g,
void gk20a_gr_suspend_all_sms(struct gk20a *g,
u32 global_esr_mask, bool check_errors);
u32 gr_gk20a_get_tpc_count(struct gr_gk20a *gr, u32 gpc_index);
int gk20a_gr_lock_down_sm(struct gk20a *g,
u32 gpc, u32 tpc, u32 global_esr_mask,
bool check_errors);

1
drivers/gpu/nvgpu/gm20b/gr_gm20b.c
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@@ -1632,4 +1632,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel;
gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached;
gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm;
gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms;
}

4
drivers/gpu/nvgpu/gp10b/gr_gp10b.c
View File

@@ -1822,7 +1822,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g,
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
"CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n",
gpc, tpc);
gk20a_suspend_all_sms(g, global_mask, false);
g->ops.gr.suspend_all_sms(g, global_mask, false);
gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch);
} else {
@@ -1991,7 +1991,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
*cilp_preempt_pending = false;
if (gk20a_is_channel_ctx_resident(ch)) {
gk20a_suspend_all_sms(g, 0, false);
g->ops.gr.suspend_all_sms(g, 0, false);
if (gr_ctx->compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP) {
err = gr_gp10b_set_cilp_preempt_pending(g, ch);