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gpu: nvgpu: vgpu: dbg_set_powergate support
Add support for dbg_set_powergate when virtualized Jira VFND-1905 Change-Id: I0d81c8863b3eda4ae4fee42e5a95d2fc9d78b174 Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1162048 (cherry picked from commit 0dfc55f390a10e21ae13e14dd2f16e89a3bddfa7) Reviewed-on: http://git-master/r/1167182 (cherry picked from commit 4e34a1844558d93da5ad208532ec28aeda228f95) Reviewed-on: http://git-master/r/1174701 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
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committed by
Vladislav Buzov
parent
da4d5130e8
commit
1b04326f40
@@ -96,6 +96,7 @@ enum {
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TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57,
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TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
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TEGRA_VGPU_CMD_READ_PTIMER = 59,
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TEGRA_VGPU_CMD_SET_POWERGATE = 60,
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};
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struct tegra_vgpu_connect_params {
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@@ -394,6 +395,10 @@ struct tegra_vgpu_read_ptimer_params {
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u64 time;
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};
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struct tegra_vgpu_set_powergate_params {
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u32 mode;
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};
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struct tegra_vgpu_cmd_msg {
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u32 cmd;
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int ret;
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@@ -435,6 +440,7 @@ struct tegra_vgpu_cmd_msg {
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struct tegra_vgpu_tsg_timeslice_params tsg_timeslice;
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struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave;
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struct tegra_vgpu_read_ptimer_params read_ptimer;
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struct tegra_vgpu_set_powergate_params set_powergate;
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char padding[192];
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} params;
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};
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