gpu: nvgpu: make mssnvlink programming OS agnositc

Make ga10b_init_nvlink_soc_credits OS agnostic by replacing OS
specific functions with corresponding nvgpu wrappers. This function is now
assigned to gops.mssnvlink.init_soc_credits HAL.

Introduce nvgpu wrapper, nvgpu_io_map/unmap to map/unmap specified
physical address range.

Jira NVGPU-6641

Change-Id: I337bc75b8ec36552fe471bf5e42f62c19f67ed4a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618237
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

arch/nvgpu-hal-new.yaml

@@ -1049,3 +1049,10 @@ sim:
   owner: Antony Alex
   sources: [ hal/sim/sim_ga10b.h,
              hal/sim/sim_ga10b.c ]
+
+mssnvlink:
+  safe: no
+  owner: Antony Alex
+  sources: [ include/nvgpu/gops/mssnvlink.h,
+             hal/mssnvlink/mssnvlink_ga10b.h,
+             hal/mssnvlink/mssnvlink_ga10b.c ]

arch/nvgpu-linux.yaml

@@ -186,8 +186,7 @@ platform:
              os/linux/platform_gp10b.h,
              os/linux/platform_gp10b_tegra.c,
              os/linux/platform_gv11b_tegra.c,
-             os/linux/platform_ga10b_tegra.c,
-             os/linux/nvlink/hal/ga10b_mssnvlink.c ]
+             os/linux/platform_ga10b_tegra.c ]
 
 rwsem:
   sources: [ os/linux/rwsem.c ]

drivers/gpu/nvgpu/Makefile

@@ -815,7 +815,8 @@ nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
 	hal/regops/regops_tu104.o \
 	hal/regops/allowlist_tu104.o \
 	hal/therm/therm_gm20b.o \
-	hal/top/top_gm20b.o
+	hal/top/top_gm20b.o \
+	hal/mssnvlink/mssnvlink_ga10b.o
 
 ifeq ($(CONFIG_NVGPU_GR_VIRTUALIZATION),y)
 nvgpu-$(CONFIG_NVGPU_HAL_NON_FUSA) += \
@@ -952,5 +953,4 @@ endif
 endif
 
 nvgpu-y += \
-	os/linux/platform_ga10b_tegra.o \
-	os/linux/nvlink/hal/ga10b_mssnvlink.o
+	os/linux/platform_ga10b_tegra.o

drivers/gpu/nvgpu/Makefile.sources

@@ -349,7 +349,8 @@ srcs += hal/init/hal_gp10b.c \
 	hal/top/top_gp10b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
 	hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c \
-	hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c
+	hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c \
+	hal/mssnvlink/mssnvlink_ga10b.c
 else
 ifeq ($(CONFIG_NVGPU_DGPU),1)
 # non-FUSA files needed to build dGPU in safety

drivers/gpu/nvgpu/hal/fb/fb_ga10b.h

@@ -37,16 +37,6 @@ void ga10b_fb_dump_vpr_info(struct gk20a *g);
 void ga10b_fb_dump_wpr_info(struct gk20a *g);
 void ga10b_fb_read_wpr_info(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
 int ga10b_fb_vpr_info_fetch(struct gk20a *g);
-#if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-#if defined(__KERNEL__)
-void ga10b_init_nvlink_soc_credits(struct gk20a *g);
-#else
-static inline void ga10b_init_nvlink_soc_credits(struct gk20a *g)
-{
-
-}
-#endif
-#endif
 
 #ifdef CONFIG_NVGPU_COMPRESSION
 void ga10b_fb_cbc_configure(struct gk20a *g, struct nvgpu_cbc *cbc);

drivers/gpu/nvgpu/hal/fb/fb_ga10b_fusa.c

@@ -150,7 +150,7 @@ void ga10b_fb_init_fs_state(struct gk20a *g)
 	nvgpu_log(g, gpu_dbg_fn, "initialize ga10b fb");
 
 #if defined(CONFIG_NVGPU_HAL_NON_FUSA)
-	ga10b_init_nvlink_soc_credits(g);
+	g->ops.mssnvlink.init_soc_credits(g);
 #endif
 	ga10b_fb_check_ltcs_count(g);
 

drivers/gpu/nvgpu/hal/init/hal_ga10b.c

@@ -250,6 +250,9 @@
 #include "hal/tpc/tpc_gv11b.h"
 #endif
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+#include "hal/mssnvlink/mssnvlink_ga10b.h"
+#endif
 #include "hal_ga10b.h"
 #include "hal_ga10b_litter.h"
 
@@ -1673,6 +1676,12 @@ static const struct gops_grmgr ga10b_ops_grmgr = {
 	.discover_gpc_ids = ga10b_grmgr_discover_gpc_ids,
 };
 
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+static const struct gops_mssnvlink ga10b_ops_mssnvlink = {
+	.init_soc_credits = ga10b_mssnvlink_init_soc_credits
+};
+#endif
+
 int ga10b_init_hal(struct gk20a *g)
 {
 	struct gpu_ops *gops = &g->ops;
@@ -1923,6 +1932,10 @@ int ga10b_init_hal(struct gk20a *g)
 		gops->fb.mem_unlock = NULL;
 	}
 
+#endif
+
+#ifdef CONFIG_NVGPU_HAL_NON_FUSA
+	gops->mssnvlink = ga10b_ops_mssnvlink;
 #endif
 	g->name = "ga10b";
 

drivers/gpu/nvgpu/hal/mssnvlink/mssnvlink_ga10b.c

@@ -1,17 +1,23 @@
 /*
  * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
  *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
  */
 
 #include <nvgpu/log.h>
@@ -19,8 +25,8 @@
 #include <nvgpu/io.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/soc.h>
-#include <os/linux/module.h>
-#include <os/linux/os_linux.h>
+
+#include "mssnvlink_ga10b.h"
 
 #define MSS_NVLINK_INTERNAL_NUM                 8U
 #define MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0      0x00000010
@@ -38,11 +44,10 @@
 #define MSS_NVLINK_INIT_CREDITS                 0x00000001U
 #define MSS_NVLINK_FORCE_COH_SNP		0x3U
 
-void ga10b_init_nvlink_soc_credits(struct gk20a *g)
+void ga10b_mssnvlink_init_soc_credits(struct gk20a *g)
 {
 	u32 i = 0U;
 	u32 val = MSS_NVLINK_INIT_CREDITS;
-	struct device *dev = dev_from_gk20a(g);
 
 	u32 nvlink_base[MSS_NVLINK_INTERNAL_NUM] = {
 		MSS_NVLINK_1_BASE, MSS_NVLINK_2_BASE, MSS_NVLINK_3_BASE,
@@ -50,7 +55,7 @@ void ga10b_init_nvlink_soc_credits(struct gk20a *g)
 		MSS_NVLINK_7_BASE, MSS_NVLINK_8_BASE
 	};
 
-	void __iomem *mssnvlink_control[MSS_NVLINK_INTERNAL_NUM];
+	uintptr_t mssnvlink_control[MSS_NVLINK_INTERNAL_NUM];
 
 	if (nvgpu_platform_is_simulation(g)) {
 		nvgpu_log(g, gpu_dbg_info, "simulation platform: "
@@ -65,14 +70,14 @@ void ga10b_init_nvlink_soc_credits(struct gk20a *g)
 	}
 	/* init nvlink soc credits and force snoop */
 	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
-		mssnvlink_control[i] = nvgpu_devm_ioremap(dev,
-			nvlink_base[i], MSS_NVLINK_SIZE);
+		mssnvlink_control[i] = nvgpu_io_map(g, nvlink_base[i],
+				MSS_NVLINK_SIZE);
 	}
 
 	nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits");
 
 	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
-		writel_relaxed(val, (*(mssnvlink_control + i) +
+		nvgpu_os_writel(val, (*(mssnvlink_control + i) +
 				 MSS_NVLINK_GLOBAL_CREDIT_CONTROL_0));
 	}
 
@@ -83,11 +88,11 @@ void ga10b_init_nvlink_soc_credits(struct gk20a *g)
 	nvgpu_log(g, gpu_dbg_info, "set force snoop");
 
 	for (i = 0U; i < MSS_NVLINK_INTERNAL_NUM; i++) {
-		val = readl_relaxed((*(mssnvlink_control + i) +
+		val = nvgpu_os_readl((*(mssnvlink_control + i) +
 			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0));
 		val &= ~(MSS_NVLINK_FORCE_COH_SNP);
 		val |= MSS_NVLINK_FORCE_COH_SNP;
-		writel_relaxed(val, *(mssnvlink_control + i) +
+		nvgpu_os_writel(val, *(mssnvlink_control + i) +
 			MSS_NVLINK_MCF_MEMORY_TYPE_CONTROL_0);
 	}
 }

drivers/gpu/nvgpu/hal/mssnvlink/mssnvlink_ga10b.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_MSSNVLINK_GA10B_H
+#define NVGPU_MSSNVLINK_GA10B_H
+
+struct gk20a;
+
+void ga10b_mssnvlink_init_soc_credits(struct gk20a *g);
+
+#endif /* NVGPU_MSSNVLINK_GA10B_H */

drivers/gpu/nvgpu/include/nvgpu/gops/mssnvlink.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_GOPS_MSSNVLINK_H
+#define NVGPU_GOPS_MSSNVLINK_H
+
+#include <nvgpu/types.h>
+
+/**
+ * @file
+ *
+ * MSSNVLINK unit HAL interface
+ *
+ */
+struct gk20a;
+
+/**
+ * MSSNVLINK unit HAL operations
+ *
+ * @see gpu_ops
+ */
+struct gops_mssnvlink {
+	void (*init_soc_credits)(struct gk20a *g);
+};
+
+#endif /* NVGPU_GOPS_MSSNVLINK_H */

drivers/gpu/nvgpu/include/nvgpu/gpu_ops.h

@@ -71,6 +71,9 @@
 #include <nvgpu/gops/ecc.h>
 #include <nvgpu/gops/grmgr.h>
 #include <nvgpu/gops/cic_mon.h>
+#ifdef CONFIG_NVGPU_NON_FUSA
+#include <nvgpu/gops/mssnvlink.h>
+#endif
 
 struct gk20a;
 struct nvgpu_debug_context;
@@ -226,6 +229,12 @@ struct gpu_ops {
 	struct gops_grmgr grmgr;
 
 	struct gops_cic_mon cic_mon;
+
+/** @cond DOXYGEN_SHOULD_SKIP_THIS */
+#ifdef CONFIG_NVGPU_NON_FUSA
+	struct gops_mssnvlink mssnvlink;
+#endif
+/** @endcond */
 };
 
 #endif /* NVGPU_GOPS_OPS_H */

drivers/gpu/nvgpu/include/nvgpu/io.h

@@ -24,13 +24,15 @@
 
 #include <nvgpu/types.h>
 
+struct gk20a;
+
 /**
  * @brief Read a value from a register.
  *
  * @param addr [in]		Register cpu virtual address.
  *
  * Read a 32-bit value from the register cpu virtuall address.
- * OS layer much implement this function.
+ * OS layer must implement this function.
  *
  * @return Value of the given register.
  */
@@ -43,7 +45,7 @@ u32 nvgpu_os_readl(uintptr_t addr);
  *
  * Write a 32-bit value to the register cpu virtual address with an
  * ordering constraint on memory operations.
- * OS layer much implement this function.
+ * OS layer must implement this function.
  *
  * @return None.
  */
@@ -56,12 +58,39 @@ void nvgpu_os_writel(u32 v, uintptr_t addr);
  *
  * Write a 32-bit value to the register cpu virtual address without an
  * ordering constraint on memory operations.
- * OS layer much implement this function.
+ * OS layer must implement this function.
  *
  * @return None.
  */
 void nvgpu_os_writel_relaxed(u32 v, uintptr_t addr);
 
+/**
+ * @brief Create a virtual mapping for the specified physical address range.
+ *
+ * @param g [in]	The GPU driver structure.
+ * @param addr [in]	Physical address start.
+ * @param size [in]	Physical address range.
+ *
+ * Maps the specified physical address range into the kernel/process address
+ * space. OS layer must implement this function.
+ *
+ * @return Virtual address which maps to the physical address range.
+ */
+uintptr_t nvgpu_io_map(struct gk20a *g, uintptr_t addr, size_t size);
+
+/**
+ * @brief Unmap an already mapped io-region.
+ *
+ * @param g[in]		GPU super structure.
+ * @param addr[in]	Start virtual address of the io-region.
+ * @param size[in]	Size of the io-region.
+ *
+ * - OS layer must implement this function.
+ *
+ * @return None.
+ */
+void nvgpu_io_unmap(struct gk20a *g, uintptr_t ptr, size_t size);
+
 /**
  * @file
  *

drivers/gpu/nvgpu/os/linux/linux-io.c

@@ -11,6 +11,7 @@
  * more details.
  */
 
+#include <linux/io.h>
 #include <nvgpu/io.h>
 
 #include "os_linux.h"
@@ -29,3 +30,13 @@ void nvgpu_os_writel_relaxed(u32 v, uintptr_t addr)
 {
 	writel_relaxed(v, (void __iomem *)addr);
 }
+
+uintptr_t nvgpu_io_map(struct gk20a *g, uintptr_t addr, size_t size)
+{
+	return (uintptr_t)devm_ioremap(dev_from_gk20a(g), addr, size);
+}
+
+void nvgpu_io_unmap(struct gk20a *g, uintptr_t addr, size_t size)
+{
+	devm_iounmap(dev_from_gk20a(g), (void __iomem *)addr);
+}