gpu: nvgpu: Add gv11b recovery profiling

Add some basic profiling to the gv11b recovery sequence. This captures
the high level events. Subsequent patches start to dig into the
subsections in more detail.

JIRA NVGPU-5606

Change-Id: I488a448ca1cbf961651588e24685e2a5b4420c44
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2368302
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Alex Waterman
2020-06-29 11:20:31 -05:00
parent 811ba85dc6
commit 1bcdc306a0
5 changed files with 59 additions and 0 deletions

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@@ -42,6 +42,10 @@ static const char *nvgpu_fifo_kickoff_profile_events[] = {
NVGPU_FIFO_KICKOFF_PROFILE_EVENTS,
};
static const char *nvgpu_fifo_recovery_profile_events[] = {
NVGPU_FIFO_RECOVERY_PROFILE_EVENTS,
};
void nvgpu_fifo_cleanup_sw_common(struct gk20a *g)
{
struct nvgpu_fifo *f = &g->fifo;
@@ -101,6 +105,8 @@ int nvgpu_fifo_setup_sw_common(struct gk20a *g)
nvgpu_swprofile_initialize(g, &f->kickoff_profiler,
nvgpu_fifo_kickoff_profile_events);
nvgpu_swprofile_initialize(g, &f->recovery_profiler,
nvgpu_fifo_recovery_profile_events);
err = nvgpu_channel_setup_sw(g);
if (err != 0) {

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@@ -35,6 +35,8 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include <nvgpu/nvgpu_err.h>
#include <nvgpu/swprofile.h>
#include <nvgpu/fifo/swprofile.h>
#include <nvgpu/power_features/power_features.h>
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/preempt.h>
@@ -151,11 +153,14 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
struct nvgpu_runlist_info *runlist = NULL;
u32 engine_id;
struct nvgpu_fifo *f = &g->fifo;
struct nvgpu_swprofiler *prof = &f->recovery_profiler;
#ifdef CONFIG_NVGPU_DEBUGGER
u32 client_type = ~U32(0U);
bool deferred_reset_pending = false;
#endif
nvgpu_swprofile_begin_sample(prof);
nvgpu_log_info(g, "acquire engines_reset_mutex");
nvgpu_mutex_acquire(&f->engines_reset_mutex);
@@ -163,6 +168,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
nvgpu_log_fn(g, "acquire runlist_lock for active runlists");
nvgpu_runlist_lock_active_runlists(g);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_ACQ_ACTIVE_RL);
g->ops.fifo.intr_set_recover_mask(g);
/* get tsg */
@@ -205,6 +212,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
runlists_mask = nvgpu_runlist_get_runlists_mask(g, id, id_type,
act_eng_bitmask, pbdma_bitmask);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_GET_RL_MASK);
/*
* release runlist lock for the runlists that are not
* being recovered
@@ -214,6 +223,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
/* Disable runlist scheduler */
nvgpu_runlist_set_state(g, runlists_mask, RUNLIST_DISABLED);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_DISABLE_RL);
#ifdef CONFIG_NVGPU_NON_FUSA
if (nvgpu_cg_pg_disable(g) != 0) {
nvgpu_warn(g, "fail to disable power mgmt");
@@ -232,6 +243,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
g->ops.tsg.disable(tsg);
}
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_DISABLE_TSG);
/*
* Even though TSG preempt timed out, the RC sequence would by design
* require s/w to issue another preempt.
@@ -242,6 +255,9 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
* reset.
*/
nvgpu_fifo_preempt_runlists_for_rc(g, runlists_mask);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_PREEMPT_RL);
/*
* For each PBDMA which serves the runlist, poll to verify the TSG is no
* longer on the PBDMA and the engine phase of the preempt has started.
@@ -254,6 +270,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
return;
}
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_POLL_TSG_ON_PBDMA);
#ifdef CONFIG_NVGPU_DEBUGGER
nvgpu_mutex_acquire(&f->deferred_reset_mutex);
g->fifo.deferred_reset_pending = false;
@@ -302,6 +320,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
}
}
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_ENGINES_RESET);
#ifdef CONFIG_NVGPU_FECS_TRACE
if (tsg != NULL)
nvgpu_gr_fecs_trace_add_tsg_reset(g, tsg);
@@ -324,6 +344,8 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
nvgpu_runlist_set_state(g, runlists_mask, RUNLIST_ENABLED);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_ENABLE_RL);
#ifdef CONFIG_NVGPU_NON_FUSA
if (nvgpu_cg_pg_enable(g) != 0) {
nvgpu_warn(g, "fail to enable power mgmt");
@@ -337,4 +359,6 @@ void gv11b_fifo_recover(struct gk20a *g, u32 act_eng_bitmask,
nvgpu_log_info(g, "release engines_reset_mutex");
nvgpu_mutex_release(&f->engines_reset_mutex);
nvgpu_swprofile_snapshot(prof, PROF_RECOVERY_DONE);
}

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@@ -289,6 +289,7 @@ struct nvgpu_fifo {
u32 num_runlists;
struct nvgpu_swprofiler kickoff_profiler;
struct nvgpu_swprofiler recovery_profiler;
#ifdef CONFIG_NVGPU_USERD
struct nvgpu_mutex userd_mutex;

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@@ -47,4 +47,31 @@
#define PROF_KICKOFF_END 4U
#define PROF_KICKOFF_IOCTL_EXIT 5U
/*
* Recovery profiling - this covers the gv11b+ recovery sequence; the older recovery
* sequence is very different.
*/
#define NVGPU_FIFO_RECOVERY_PROFILE_EVENTS \
"acq_active_rl", \
"get_rl_mask", \
"disable_rl", \
"disable_tsg", \
"preempt_rl", \
"poll_tsg_on_pbdma", \
"engines_reset", \
"enable_rl", \
"done", \
NULL
#define PROF_RECOVERY_ACQ_ACTIVE_RL 0U
#define PROF_RECOVERY_GET_RL_MASK 1U
#define PROF_RECOVERY_DISABLE_RL 2U
#define PROF_RECOVERY_DISABLE_TSG 3U
#define PROF_RECOVERY_PREEMPT_RL 4U
#define PROF_RECOVERY_POLL_TSG_ON_PBDMA 5U
#define PROF_RECOVERY_ENGINES_RESET 6U
#define PROF_RECOVERY_ENABLE_RL 7U
#define PROF_RECOVERY_DONE 8U
#endif

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@@ -151,4 +151,5 @@ void gk20a_fifo_debugfs_init(struct gk20a *g)
&gk20a_fifo_sched_debugfs_fops);
nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.kickoff_profiler, "kickoff_profiler");
nvgpu_debugfs_swprofile_init(g, fifo_root, &g->fifo.recovery_profiler, "recovery_profiler");
}