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gpu: nvgpu: move chip specific fuse to hal

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Move chip specific fuse code from common/fuse to hal/fuse.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define

JIRA NVGPU-2035

Change-Id: Icaa908db036053d5e6f4ff20b9e5b1d6c0ab2fda
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033278
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-05 15:17:49 -08:00
committed by mobile promotions
parent 5222d0ff4f
commit 1c3fbd9dc7
18 changed files with 52 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/Makefile
View File

@@ -48,9 +48,6 @@ nvgpu-y += \
common/therm/therm_gp10b.o \
common/therm/therm_gp106.o \
common/therm/therm_gv11b.o \
common/fuse/fuse_gm20b.o \
common/fuse/fuse_gp10b.o \
common/fuse/fuse_gp106.o \
common/top/top_gm20b.o \
common/top/top_gp10b.o \
common/top/top_gv100.o \
@@ -176,7 +173,10 @@ nvgpu-y += \
hal/cg/gp10b_gating_reglist.o \
hal/cg/gv100_gating_reglist.o \
hal/cg/gv11b_gating_reglist.o \
hal/cg/tu104_gating_reglist.o
hal/cg/tu104_gating_reglist.o \
hal/fuse/fuse_gm20b.o \
hal/fuse/fuse_gp10b.o \
hal/fuse/fuse_gp106.o
# Linux specific parts of nvgpu.
nvgpu-y += \

8
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -93,9 +93,6 @@ srcs += common/sim.c \
common/perf/perf_gv11b.c \
common/perf/perfbuf.c \
common/perf/cyclestats_snapshot.c \
common/fuse/fuse_gm20b.c \
common/fuse/fuse_gp10b.c \
common/fuse/fuse_gp106.c \
common/top/top_gm20b.c \
common/top/top_gp10b.c \
common/top/top_gv100.c \
@@ -336,7 +333,10 @@ srcs += common/sim.c \
hal/cg/gv11b_gating_reglist.c \
hal/cg/gp106_gating_reglist.c \
hal/cg/gv100_gating_reglist.c \
hal/cg/tu104_gating_reglist.c
hal/cg/tu104_gating_reglist.c \
hal/fuse/fuse_gm20b.c \
hal/fuse/fuse_gp10b.c \
hal/fuse/fuse_gp106.c
ifeq ($(NVGPU_DEBUGGER),1)
srcs += common/debugger.c

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -35,8 +35,6 @@
#include "common/perf/perf_gm20b.h"
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/regops/regops_gp10b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/channel_gm20b.h"

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -38,8 +38,6 @@
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/ltc/ltc_gv11b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -41,6 +41,7 @@
#include "hal/bus/bus_gk20a.h"
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/cg/gm20b_gating_reglist.h"
#include "hal/fuse/fuse_gm20b.h"
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
@@ -50,7 +51,6 @@
#include "common/gr/zbc/gr_zbc_gm20b.h"
#include "common/therm/therm_gm20b.h"
#include "common/ltc/ltc_gm20b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/mc/mc_gm20b.h"
#include "common/perf/perf_gm20b.h"
#include "common/pmu/pmu_gk20a.h"

4
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -45,6 +45,8 @@
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/cg/gp10b_gating_reglist.h"
#include "hal/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gp10b.h"
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
@@ -59,8 +61,6 @@
#include "common/therm/therm_gp10b.h"
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/perf/perf_gm20b.h"

6
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -28,6 +28,9 @@
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/cg/gv100_gating_reglist.h"
#include "hal/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gp10b.h"
#include "hal/fuse/fuse_gp106.h"
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
@@ -51,9 +54,6 @@
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/ltc/ltc_gv11b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/fuse/fuse_gp106.h"
#include "common/top/top_gm20b.h"
#include "common/top/top_gp10b.h"
#include "common/top/top_gv100.h"

4
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -31,6 +31,8 @@
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/cg/gv11b_gating_reglist.h"
#include "hal/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gp10b.h"
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
@@ -51,8 +53,6 @@
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/ltc/ltc_gv11b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/mc/mc_gv11b.h"

6
drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c → drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.c
View File

@@ -52,7 +52,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
if (gk20a_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
if (nvgpu_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
/*
* all falcons have to boot in LS mode and this needs
* wpr_enabled set to 1 and vpr_auto_fetch_disable
@@ -65,7 +65,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g)
is_auto_fetch_disable =
(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
if (is_wpr_enabled && !is_auto_fetch_disable) {
if (gk20a_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
if (nvgpu_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR debug",
@@ -130,5 +130,5 @@ u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g)
u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g)
{
return gk20a_readl(g, fuse_opt_priv_sec_en_r());
return nvgpu_readl(g, fuse_opt_priv_sec_en_r());
}

2
drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h → drivers/gpu/nvgpu/hal/fuse/fuse_gm20b.h
View File

@@ -1,7 +1,7 @@
/*
* GM20B FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

40
drivers/gpu/nvgpu/common/fuse/fuse_gp106.c → drivers/gpu/nvgpu/hal/fuse/fuse_gp106.c
View File

@@ -33,7 +33,7 @@
u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g)
{
return fuse_vin_cal_fuse_rev_data_v(
gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
nvgpu_readl(g, fuse_vin_cal_fuse_rev_r()));
}
static int gp106_compute_slope_intercept_data(struct gk20a *g,
@@ -47,8 +47,8 @@ static int gp106_compute_slope_intercept_data(struct gk20a *g,
bool error_status = false;
/* read gpc0 irrespective of vin id */
gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == 0xFFFFFFFFU) {
gpc0data = nvgpu_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == U32_MAX) {
return -EINVAL;
}
@@ -113,8 +113,8 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
int status = 0;
/* read gpc0 irrespective of vin id */
gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == 0xFFFFFFFFU) {
gpc0data = nvgpu_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == U32_MAX) {
return -EINVAL;
}
@@ -123,29 +123,29 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
break;
case CTRL_CLK_VIN_ID_GPC1:
data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_gpc1_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC2:
data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_gpc2_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC3:
data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_gpc3_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC4:
data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_gpc4_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC5:
data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_gpc5_delta_r());
break;
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
data = nvgpu_readl(g, fuse_vin_cal_shared_delta_r());
break;
default:
@@ -156,7 +156,7 @@ int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
if (error_status == true) {
return -EINVAL;
}
if (data == 0xFFFFFFFFU) {
if (data == U32_MAX) {
return -EINVAL;
}
@@ -185,33 +185,33 @@ int gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
switch (vin_id) {
case CTRL_CLK_VIN_ID_GPC0:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc0_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc0_r());
break;
case CTRL_CLK_VIN_ID_GPC1:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc1_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC2:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc2_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC3:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc3_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC4:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc4_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC5:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_gpc5_delta_r());
break;
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
reg_val = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
reg_val = nvgpu_readl(g, fuse_vin_cal_shared_delta_r());
break;
default:
@@ -222,7 +222,7 @@ int gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
if (error_status == true) {
return -EINVAL;
}
if (reg_val == 0xFFFFFFFFU) {
if (reg_val == U32_MAX) {
return -EINVAL;
}
data = (reg_val >> 16U) & 0x1fU;

2
drivers/gpu/nvgpu/common/fuse/fuse_gp106.h → drivers/gpu/nvgpu/hal/fuse/fuse_gp106.h
View File

@@ -1,7 +1,7 @@
/*
* GP106 FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

8
drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c → drivers/gpu/nvgpu/hal/fuse/fuse_gp10b.c
View File

@@ -51,7 +51,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
return -EINVAL;
}
if (gk20a_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
if (nvgpu_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
/*
* all falcons have to boot in LS mode and this needs
* wpr_enabled set to 1 and vpr_auto_fetch_disable
@@ -65,7 +65,7 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
is_auto_fetch_disable =
(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
if (is_wpr_enabled && !is_auto_fetch_disable) {
if (gk20a_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
if (nvgpu_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR debug",
@@ -97,11 +97,11 @@ int gp10b_fuse_check_priv_security(struct gk20a *g)
bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g)
{
return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U;
return nvgpu_readl(g, fuse_opt_ecc_en_r()) != 0U;
}
bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
{
return gk20a_readl(g,
return nvgpu_readl(g,
fuse_opt_feature_fuses_override_disable_r()) != 0U;
}

2
drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h → drivers/gpu/nvgpu/hal/fuse/fuse_gp10b.h
View File

@@ -1,7 +1,7 @@
/*
* GP10B FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),

6
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -29,6 +29,9 @@
#include "hal/priv_ring/priv_ring_gm20b.h"
#include "hal/priv_ring/priv_ring_gp10b.h"
#include "hal/cg/tu104_gating_reglist.h"
#include "hal/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gp10b.h"
#include "hal/fuse/fuse_gp106.h"
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
@@ -55,9 +58,6 @@
#include "common/ltc/ltc_gp10b.h"
#include "common/ltc/ltc_gv11b.h"
#include "common/ltc/ltc_tu104.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/fuse/fuse_gp106.h"
#include "common/mc/mc_gm20b.h"
#include "common/mc/mc_gp10b.h"
#include "common/mc/mc_gv11b.h"

2
userspace/units/fuse/nvgpu-fuse-gm20b.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/fuse.h>
#include <nvgpu/hal_init.h>
#include "common/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gm20b.h"
#include "nvgpu-fuse-priv.h"
#include "nvgpu-fuse-gm20b.h"

2
userspace/units/fuse/nvgpu-fuse-gp10b.c
View File

@@ -25,7 +25,7 @@
#include <nvgpu/posix/io.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/fuse.h>
#include "common/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gm20b.h"
#include "nvgpu-fuse-priv.h"
#include "nvgpu-fuse-gp10b.h"

2
userspace/units/fuse/nvgpu-fuse-gv100.c
View File

@@ -27,7 +27,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/fuse.h>
#include <nvgpu/hal_init.h>
#include "common/fuse/fuse_gm20b.h"
#include "hal/fuse/fuse_gm20b.h"
#include "nvgpu-fuse-priv.h"
#include "nvgpu-fuse-gv100.h"