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gpu: nvgpu: move chip specific fuse to hal

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Move chip specific fuse code from common/fuse to hal/fuse.
Replace gk20a_readl/writel with nvgpu_readl/writel
Replace 0xFFFFFFFFU with U32_MAX hash define

JIRA NVGPU-2035

Change-Id: Icaa908db036053d5e6f4ff20b9e5b1d6c0ab2fda
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033278
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-03-05 15:17:49 -08:00
committed by mobile promotions
parent 5222d0ff4f
commit 1c3fbd9dc7
18 changed files with 52 additions and 56 deletions
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134
drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
View File

@@ -1,134 +0,0 @@
/*
* GM20B FUSE
*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/fuse.h>
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "fuse_gm20b.h"
#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
int gm20b_fuse_check_priv_security(struct gk20a *g)
{
u32 gcplex_config;
bool is_wpr_enabled = false;
bool is_auto_fetch_disable = false;
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel");
return 0;
}
if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
return -EINVAL;
}
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
if (gk20a_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
/*
* all falcons have to boot in LS mode and this needs
* wpr_enabled set to 1 and vpr_auto_fetch_disable
* set to 0. In this case gmmu tries to pull wpr
* and vpr settings from tegra mc
*/
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
is_wpr_enabled =
(gcplex_config & GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
is_auto_fetch_disable =
(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
if (is_wpr_enabled && !is_auto_fetch_disable) {
if (gk20a_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR debug",
gcplex_config);
} else {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR non debug",
gcplex_config);
}
} else {
nvgpu_err(g, "gcplex_config = 0x%08x "
"invalid wpr_enabled/vpr_auto_fetch_disable "
"with priv_sec_en", gcplex_config);
/* do not try to boot GPU */
return -EINVAL;
}
} else {
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, non secure mode",
gcplex_config);
}
return 0;
}
u32 gm20b_fuse_status_opt_fbio(struct gk20a *g)
{
return nvgpu_readl(g, fuse_status_opt_fbio_r());
}
u32 gm20b_fuse_status_opt_fbp(struct gk20a *g)
{
return nvgpu_readl(g, fuse_status_opt_fbp_r());
}
u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
{
return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
}
u32 gm20b_fuse_status_opt_gpc(struct gk20a *g)
{
return nvgpu_readl(g, fuse_status_opt_gpc_r());
}
u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
{
return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
}
void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val)
{
nvgpu_writel(g, fuse_ctrl_opt_tpc_gpc_r(gpc), val);
}
u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g)
{
return nvgpu_readl(g, fuse_opt_sec_debug_en_r());
}
u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g)
{
return gk20a_readl(g, fuse_opt_priv_sec_en_r());
}

45
drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
View File

@@ -1,45 +0,0 @@
/*
* GM20B FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FUSE_GM20B_H
#define NVGPU_FUSE_GM20B_H
#define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK BIT32(0)
#define GCPLEX_CONFIG_VPR_ENABLED_MASK BIT32(1)
#define GCPLEX_CONFIG_WPR_ENABLED_MASK BIT32(2)
struct gk20a;
int gm20b_fuse_check_priv_security(struct gk20a *g);
u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
u32 gm20b_fuse_opt_priv_sec_en(struct gk20a *g);
#endif /* NVGPU_FUSE_GM20B_H */

234
drivers/gpu/nvgpu/common/fuse/fuse_gp106.c
View File

@@ -1,234 +0,0 @@
/*
* GP106 FUSE
*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "fuse_gp106.h"
#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g)
{
return fuse_vin_cal_fuse_rev_data_v(
gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
}
static int gp106_compute_slope_intercept_data(struct gk20a *g,
u32 vin_id, u32 *slope, u32 *intercept,
u32 data, u32 gpc0interceptdata){
u32 interceptdata = 0U;
u32 slopedata = 0U;
u32 gpc0data = 0U;
u32 gpc0slopedata = 0U;
bool error_status = false;
/* read gpc0 irrespective of vin id */
gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == 0xFFFFFFFFU) {
return -EINVAL;
}
switch (vin_id) {
case CTRL_CLK_VIN_ID_GPC0:
break;
case CTRL_CLK_VIN_ID_GPC1:
case CTRL_CLK_VIN_ID_GPC2:
case CTRL_CLK_VIN_ID_GPC3:
case CTRL_CLK_VIN_ID_GPC4:
case CTRL_CLK_VIN_ID_GPC5:
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
interceptdata = (interceptdata * 1000U) >>
fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
slopedata = (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) *
1000U;
break;
default:
error_status = true;
break;
}
if (error_status == true) {
return -EINVAL;
}
if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data) != 0U) {
*intercept = gpc0interceptdata - interceptdata;
} else {
*intercept = gpc0interceptdata + interceptdata;
}
/* slope */
gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
fuse_vin_cal_gpc0_slope_frac_data_s()) +
fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
gpc0slopedata = (gpc0slopedata * 1000U) >>
fuse_vin_cal_gpc0_slope_frac_data_s();
if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data) != 0U) {
*slope = gpc0slopedata - slopedata;
} else {
*slope = gpc0slopedata + slopedata;
}
return 0;
}
int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
u32 vin_id, u32 *slope,
u32 *intercept)
{
u32 data = 0U;
u32 gpc0data;
u32 gpc0interceptdata;
bool error_status = false;
int status = 0;
/* read gpc0 irrespective of vin id */
gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
if (gpc0data == 0xFFFFFFFFU) {
return -EINVAL;
}
switch (vin_id) {
case CTRL_CLK_VIN_ID_GPC0:
break;
case CTRL_CLK_VIN_ID_GPC1:
data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC2:
data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC3:
data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC4:
data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC5:
data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
break;
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
break;
default:
error_status = true;
break;
}
if (error_status == true) {
return -EINVAL;
}
if (data == 0xFFFFFFFFU) {
return -EINVAL;
}
gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
fuse_vin_cal_gpc0_icpt_frac_data_s()) +
fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
gpc0interceptdata = (gpc0interceptdata * 1000U) >>
fuse_vin_cal_gpc0_icpt_frac_data_s();
status = gp106_compute_slope_intercept_data(g, vin_id, slope,
intercept, data, gpc0interceptdata);
if (status != 0) {
return -EINVAL;
}
return status;
}
int gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
u32 vin_id, s8 *gain,
s8 *offset)
{
u32 reg_val = 0;
u32 data = 0;
bool error_status = false;
switch (vin_id) {
case CTRL_CLK_VIN_ID_GPC0:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc0_r());
break;
case CTRL_CLK_VIN_ID_GPC1:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC2:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC3:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC4:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
break;
case CTRL_CLK_VIN_ID_GPC5:
reg_val = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
break;
case CTRL_CLK_VIN_ID_SYS:
case CTRL_CLK_VIN_ID_XBAR:
case CTRL_CLK_VIN_ID_LTC:
reg_val = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
break;
default:
error_status = true;
break;
}
if (error_status == true) {
return -EINVAL;
}
if (reg_val == 0xFFFFFFFFU) {
return -EINVAL;
}
data = (reg_val >> 16U) & 0x1fU;
*gain = (s8)data;
data = reg_val & 0x7fU;
*offset = (s8)data;
return 0;
}

38
drivers/gpu/nvgpu/common/fuse/fuse_gp106.h
View File

@@ -1,38 +0,0 @@
/*
* GP106 FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FUSE_GP106_H
#define NVGPU_FUSE_GP106_H
struct gk20a;
u32 gp106_fuse_read_vin_cal_fuse_rev(struct gk20a *g);
int gp106_fuse_read_vin_cal_slope_intercept_fuse(struct gk20a *g,
u32 vin_id, u32 *slope,
u32 *intercept);
int gp106_fuse_read_vin_cal_gain_offset_fuse(struct gk20a *g,
u32 vin_id, s8 *gain,
s8 *offset);
#endif /* NVGPU_FUSE_GP106_H */

107
drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c
View File

@@ -1,107 +0,0 @@
/*
* GP10B FUSE
*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/types.h>
#include <nvgpu/fuse.h>
#include <nvgpu/enabled.h>
#include <nvgpu/io.h>
#include <nvgpu/gk20a.h>
#include "fuse_gm20b.h"
#include "fuse_gp10b.h"
#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
int gp10b_fuse_check_priv_security(struct gk20a *g)
{
u32 gcplex_config;
bool is_wpr_enabled = false;
bool is_auto_fetch_disable = false;
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel");
return 0;
}
if (g->ops.fuse.read_gcplex_config_fuse(g, &gcplex_config) != 0) {
nvgpu_err(g, "err reading gcplex config fuse, check fuse clk");
return -EINVAL;
}
if (gk20a_readl(g, fuse_opt_priv_sec_en_r()) != 0U) {
/*
* all falcons have to boot in LS mode and this needs
* wpr_enabled set to 1 and vpr_auto_fetch_disable
* set to 0. In this case gmmu tries to pull wpr
* and vpr settings from tegra mc
*/
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
is_wpr_enabled =
(gcplex_config & GCPLEX_CONFIG_WPR_ENABLED_MASK) != 0U;
is_auto_fetch_disable =
(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK) != 0U;
if (is_wpr_enabled && !is_auto_fetch_disable) {
if (gk20a_readl(g, fuse_opt_sec_debug_en_r()) != 0U) {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR debug",
gcplex_config);
} else {
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, "
"secure mode: ACR non debug",
gcplex_config);
}
} else {
nvgpu_err(g, "gcplex_config = 0x%08x "
"invalid wpr_enabled/vpr_auto_fetch_disable "
"with priv_sec_en", gcplex_config);
/* do not try to boot GPU */
return -EINVAL;
}
} else {
nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
nvgpu_log(g, gpu_dbg_info,
"gcplex_config = 0x%08x, non secure mode",
gcplex_config);
}
return 0;
}
bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g)
{
return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U;
}
bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g)
{
return gk20a_readl(g,
fuse_opt_feature_fuses_override_disable_r()) != 0U;
}

34
drivers/gpu/nvgpu/common/fuse/fuse_gp10b.h
View File

@@ -1,34 +0,0 @@
/*
* GP10B FUSE
*
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_FUSE_GP10B_H
#define NVGPU_FUSE_GP10B_H
struct gk20a;
int gp10b_fuse_check_priv_security(struct gk20a *g);
bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g);
bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g);
#endif /* NVGPU_FUSE_GP10B_H */

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -35,8 +35,6 @@
#include "common/perf/perf_gm20b.h"
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/regops/regops_gp10b.h"
#include "common/fifo/runlist_gk20a.h"
#include "common/fifo/channel_gm20b.h"

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -38,8 +38,6 @@
#include "common/ltc/ltc_gm20b.h"
#include "common/ltc/ltc_gp10b.h"
#include "common/ltc/ltc_gv11b.h"
#include "common/fuse/fuse_gm20b.h"
#include "common/fuse/fuse_gp10b.h"
#include "common/sync/syncpt_cmdbuf_gv11b.h"
#include "common/sync/sema_cmdbuf_gv11b.h"
#include "common/regops/regops_gv11b.h"