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gpu: nvgpu: Fix MISRA Rule 15.7 errors in gr/intr unit

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Fix MISRA violations for Rule 15.7 in gr/intr unit
misra_violation: No non-empty terminating "else" statement.

Jira NVGPU-3227

Change-Id: I369aa2997dc3f45f6ff3946a2febfc0a95a47d34
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113223
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-05-06 15:28:50 -07:00
committed by mobile promotions
parent 3ef3d129ee
commit 1cd29cc075
2 changed files with 16 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.c
View File

@@ -136,12 +136,14 @@ void gv11b_gr_intr_set_skedcheck(struct gk20a *g, u32 data)
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f()
);
} else if ((data & NVC397_SET_SKEDCHECK_18_MASK) ==
NVC397_SET_SKEDCHECK_18_ENABLE) {
reg_val = set_field(reg_val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()
);
} else {
if ((data & NVC397_SET_SKEDCHECK_18_MASK) ==
NVC397_SET_SKEDCHECK_18_ENABLE) {
reg_val = set_field(reg_val,
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(),
gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f()
);
}
}
nvgpu_log_info(g, "sked_hww_esr_en = 0x%x", reg_val);
nvgpu_writel(g, gr_sked_hww_esr_en_r(), reg_val);

14
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_tu104.c
View File

@@ -46,12 +46,14 @@ static void gr_tu104_set_sm_disp_ctrl(struct gk20a *g, u32 data)
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(),
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_disable_f()
);
} else if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK)
== NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) {
reg_val = set_field(reg_val,
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(),
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f()
);
} else {
if ((data & NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_MASK)
== NVC5C0_SET_SM_DISP_CTRL_COMPUTE_SHADER_QUAD_ENABLE) {
reg_val = set_field(reg_val,
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_m(),
gr_gpcs_tpcs_sm_disp_ctrl_compute_shader_quad_enable_f()
);
}
}
nvgpu_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), reg_val);