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gpu: nvgpu: add tsg_id to vgpu_gr_ctx struct
To reuse linux gr code for QNX tsg_id will be required during alloc_gr_ctx. rm-server will reuse the gr_ctx from tsg and would not allocate it. Jira VQRM-2982 Change-Id: I236deb181b89a38e70dedca4190a4275be9f0b28 Signed-off-by: Shashank Singh <shashsingh@nvidia.com> Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1659907 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-by: Sourab Gupta <sourabg@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -369,6 +369,7 @@ struct tegra_vgpu_gr_ctx_params {
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u64 as_handle;
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u64 gr_ctx_va;
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u32 class_num;
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u32 tsg_id;
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};
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struct tegra_vgpu_channel_bind_gr_ctx_params {
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@@ -302,6 +302,7 @@ int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
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p->as_handle = vm->handle;
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p->gr_ctx_va = gr_ctx->mem.gpu_va;
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p->class_num = class;
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p->tsg_id = gr_ctx->tsgid;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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@@ -501,6 +502,7 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags)
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if (!nvgpu_mem_is_valid(&gr_ctx->mem)) {
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tsg->vm = c->vm;
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nvgpu_vm_get(tsg->vm);
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gr_ctx->tsgid = tsg->tsgid;
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err = g->ops.gr.alloc_gr_ctx(g, gr_ctx,
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c->vm,
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class_num,
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