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gpu: nvgpu: fix MISRA rule 5.7 and 4.7 violations

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nvgpu_pmu_cmd_post return value was not used in some call sites in
pmu perfmon. data structures were forward declared where not reqd
are removed and header included where needed.

JIRA NVGPU-1971

Change-Id: I8714ed138d1c0b897540b624ae73c70c0a0318e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-04-09 19:30:39 +05:30
committed by mobile promotions
parent bcbc87dc2e
commit 1eb8abe0de
17 changed files with 23 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c
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@@ -197,8 +197,12 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
}
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT");
nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL);
if (status != 0) {
nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_INIT");
return status;
}
return 0;
}
@@ -256,8 +260,12 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu)
}
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START");
nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL);
if (status != 0) {
nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_START");
return status;
}
return 0;
}
@@ -267,6 +275,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu)
struct gk20a *g = pmu->g;
struct pmu_cmd cmd;
u64 tmp_size;
int status;
if (!nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) {
return 0;
@@ -285,8 +294,12 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu)
cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP;
nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP");
nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ,
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ,
NULL, NULL);
if (status != 0) {
nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_STOP");
return status;
}
return 0;
}