gpu: nvgpu: fix MISRA rule 5.7 and 4.7 violations

nvgpu_pmu_cmd_post return value was not used in some call sites in
pmu perfmon. data structures were forward declared where not reqd
are removed and header included where needed.

JIRA NVGPU-1971

Change-Id: I8714ed138d1c0b897540b624ae73c70c0a0318e0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/common/acr/acr_priv.h

@@ -27,7 +27,6 @@
 #include "acr_blob_construct_v0.h"
 #include "acr_blob_construct_v1.h"
 
-struct nvgpu_firmware;
 struct gk20a;
 struct nvgpu_acr;
 struct wpr_carveout_info;

drivers/gpu/nvgpu/common/pmu/clk/clk_freq_controller.h

@@ -23,7 +23,7 @@
 #ifndef NVGPU_CLK_FREQ_CONTROLLER_H
 #define NVGPU_CLK_FREQ_CONTROLLER_H
 
-struct boardobj;
+#include <nvgpu/boardobj.h>
 
 #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL  0xFFU
 #define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS  0x00U

drivers/gpu/nvgpu/common/pmu/perfmon/pmu_perfmon.c

@@ -197,8 +197,12 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu)
 	}
 
 	nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT");
-	nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
+	status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
 			NULL, NULL);
+	if (status != 0) {
+		nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_INIT");
+		return status;
+	}
 
 	return 0;
 }
@@ -256,8 +260,12 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu)
 	}
 
 	nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START");
-	nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
+	status = nvgpu_pmu_cmd_post(g, &cmd, &payload, PMU_COMMAND_QUEUE_LPQ,
 			NULL, NULL);
+	if (status != 0) {
+		nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_START");
+		return status;
+	}
 
 	return 0;
 }
@@ -267,6 +275,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu)
 	struct gk20a *g = pmu->g;
 	struct pmu_cmd cmd;
 	u64 tmp_size;
+	int status;
 
 	if (!nvgpu_is_enabled(g, NVGPU_PMU_PERFMON)) {
 		return 0;
@@ -285,8 +294,12 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu)
 	cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP;
 
 	nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP");
-	nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ,
+	status = nvgpu_pmu_cmd_post(g, &cmd, NULL, PMU_COMMAND_QUEUE_LPQ,
 			NULL, NULL);
+	if (status != 0) {
+		nvgpu_err(g, "failed cmd post PMU_PERFMON_CMD_ID_STOP");
+		return status;
+	}
 	return 0;
 }
 

drivers/gpu/nvgpu/common/pmu/pmu_gk20a.h

@@ -30,8 +30,6 @@
 #include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
 #include <nvgpu/pmu.h>
 
-struct nvgpu_firmware;
-
 #define ZBC_MASK(i)			U16(~(~(0U) << ((i)+1U)) & 0xfffeU)
 
 bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu);

drivers/gpu/nvgpu/common/pmu/super_surface/super_surface_priv.h

@@ -32,7 +32,6 @@
 #include <nvgpu/flcnif_cmn.h>
 
 struct nvgpu_mem;
-struct nv_pmu_super_surface_member_descriptor;
 
 /* PMU super surface */
 /* 1MB Bytes for SUPER_SURFACE_SIZE */

drivers/gpu/nvgpu/include/nvgpu/acr.h

@@ -27,7 +27,6 @@ struct gk20a;
 struct nvgpu_falcon;
 struct nvgpu_firmware;
 struct nvgpu_acr;
-struct nv_pmu_rpc_header;
 
 int nvgpu_acr_init(struct gk20a *g, struct nvgpu_acr **acr);
 int nvgpu_acr_alloc_blob_prerequisite(struct gk20a *g, struct nvgpu_acr *acr,

drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h

@@ -26,7 +26,6 @@
 struct boardobjgrp;
 struct gk20a;
 struct nvgpu_list_node;
-struct pmu_surface;
 
 
 /* ------------------------ Includes ----------------------------------------*/

drivers/gpu/nvgpu/include/nvgpu/boardobjgrpmask.h

@@ -26,9 +26,6 @@
 #include <nvgpu/types.h>
 #include <nvgpu/pmu/pmuif/ctrlboardobj.h>
 
-struct ctrl_boardobjgrp_mask;
-
-
 /*
 * Board Object Group Mask super-structure.
 * Used to unify access to all BOARDOBJGRPMASK_E** child classes

drivers/gpu/nvgpu/include/nvgpu/nvlink.h

@@ -46,7 +46,6 @@
 #define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, (g)->nvlink.links[(id)].dlpl_base + (off), (v))
 
 struct gk20a;
-struct nvgpu_firmware;
 
 struct nvgpu_nvlink_ioctrl_list {
 	bool valid;

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_domain.h

@@ -30,7 +30,6 @@
 struct gk20a;
 struct nvgpu_clk_domain;
 struct nvgpu_clk_slave_freq;
-struct ctrl_perf_change_seq_change_input;
 struct nvgpu_clk_pmupstate;
 
 typedef int nvgpu_clkproglink(struct gk20a *g, struct nvgpu_clk_pmupstate *pclk,

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_fll.h

@@ -26,13 +26,12 @@
 #define NVGPU_PMU_CLK_FLL_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/boardobjgrpmask.h>
+#include <nvgpu/pmu/pmuif/clk.h>
 
 struct gk20a;
 struct fll_device;
 struct boardobjgrp_e32;
-struct boardobjgrpmask_e32;
-struct nv_pmu_clk_lut_device_desc;
-struct nv_pmu_clk_regime_desc;
 
 struct nvgpu_avfsfllobjs {
 	struct boardobjgrp_e32 super;

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_controller.h

@@ -26,10 +26,10 @@
 #define NVGPU_PMU_CLK_FREQ_CONTROLLER_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/boardobjgrpmask.h>
 
 struct gk20a;
 struct boardobjgrp_e32;
-struct boardobjgrpmask_e32;
 
 struct nvgpu_clk_freq_controllers {
 	struct boardobjgrp_e32 super;

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_freq_domain.h

@@ -26,9 +26,9 @@
 #define NVGPU_PMU_CLK_FREQ_DOMAIN_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/boardobj.h>
 
 struct gk20a;
-struct boardobj;
 struct boardobjgrp_e32;
 
 struct nvgpu_clk_freq_domain_grp {

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vf_point.h

@@ -26,11 +26,10 @@
 #define NVGPU_PMU_CLK_VF_POINT_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/pmu/pmuif/ctrlclk.h>
 
 struct gk20a;
 struct boardobjgrp_e255;
-struct ctrl_clk_vf_pair;
-struct ctrl_clk_freq_delta;
 
 struct nvgpu_clk_vf_points {
 	struct boardobjgrp_e255 super;

drivers/gpu/nvgpu/include/nvgpu/pmu/clk/clk_vin.h

@@ -26,11 +26,11 @@
 #define NVGPU_PMU_CLK_VIN_H
 
 #include <nvgpu/types.h>
+#include <nvgpu/boardobj.h>
 
 struct gk20a;
 struct nvgpu_vin_device;
 struct nvgpu_clk_pmupstate;
-struct boardobj;
 struct boardobjgrp_e32;
 
 typedef u32 vin_device_state_load(struct gk20a *g,

drivers/gpu/nvgpu/include/nvgpu/pmu/cmd.h

@@ -40,7 +40,6 @@ struct nvgpu_pmu;
 struct pmu_msg;
 struct pmu_sequence;
 struct falcon_payload_alloc;
-struct nvgpu_engine_fb_queue;
 
 typedef void (*pmu_callback)(struct gk20a *g, struct pmu_msg *msg, void *param,
 		u32 status);

drivers/gpu/nvgpu/include/nvgpu/pmu/msg.h

@@ -45,7 +45,6 @@ struct gk20a;
 struct nvgpu_pmu;
 struct nvgpu_allocator;
 struct pmu_sequences;
-struct pmu_queues;
 struct nvgpu_mem;
 struct nvgpu_falcon;