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gpu: nvgpu: gv11b: init handle_sm_exception gr ops

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gr_gk20a_handle_sm_exception is initialized to
handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception
is initialized to gr_gv11b_handle_tpc_sm_ecc_exception
to handle sm ecc errors per tpc.

JIRA GPUT19X-75
JIRA GPUT19X-109

Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514039
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Seema Khowala
2017-06-22 14:06:18 -07:00
committed by mobile promotions
parent 99aeb5ae3b
commit 1f09340f82
1 changed files with 7 additions and 4 deletions
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11
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
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@@ -589,9 +589,10 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc,
}
static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
u32 sm, bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr)
static int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g,
u32 gpc, u32 tpc,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr)
{
int ret = 0;
@@ -3228,7 +3229,7 @@ void gv11b_init_gr(struct gpu_ops *gops)
gops->gr.init_cyclestats = gr_gv11b_init_cyclestats;
gops->gr.set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask;
gops->gr.get_access_map = gr_gv11b_get_access_map;
gops->gr.handle_sm_exception = gr_gv11b_handle_sm_exception;
gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
gops->gr.handle_gcc_exception = gr_gv11b_handle_gcc_exception;
gops->gr.handle_tex_exception = gr_gv11b_handle_tex_exception;
gops->gr.enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions;
@@ -3277,4 +3278,6 @@ void gv11b_init_gr(struct gpu_ops *gops)
gops->gr.lock_down_sm = gv11b_gr_lock_down_sm;
gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down;
gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww;
gops->gr.handle_tpc_sm_ecc_exception =
gr_gv11b_handle_tpc_sm_ecc_exception;
}