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gpu: nvgpu: remove support for quad reg_op

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quad type reg_ops were only needed on Kepler, and not for any other chip
beginning Maxweel.

HAL g->ops.gr.access_smpc_reg() was incorrectly set for Volta and Turing
whereas it was only applicable to Kepler. Delete it.

There is no register in the quad type whitelist since the type itself is
not supported anymore. Remove the empty whitelists for all chips and
also delete below HALs:
g->ops.regops.get_qctl_whitelist()
g->ops.regops.get_qctl_whitelist_count()

hal/regops/regops_gv100.* files are not used anymore. Delete the files
instead of just deleting quad HALs in these files.

Bug 200628391

Change-Id: I4dcc04bef5c24eb4d63d913f492a8c00543163a2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366035
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2020-06-18 18:22:46 +05:30
committed by Alex Waterman
parent 73ff4ac334
commit 1ff79b1d2c
26 changed files with 9 additions and 5913 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -422,8 +422,6 @@ struct gpu_ops {
u64 (*get_context_whitelist_ranges_count)(void);
const u32* (*get_runcontrol_whitelist)(void);
u64 (*get_runcontrol_whitelist_count)(void);
const u32* (*get_qctl_whitelist)(void);
u64 (*get_qctl_whitelist_count)(void);
} regops;
#endif
struct gops_mc mc;

4
drivers/gpu/nvgpu/include/nvgpu/gops_gr.h
View File

@@ -1067,7 +1067,6 @@ struct gops_gr {
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
#ifdef CONFIG_NVGPU_DEBUGGER
u32 (*get_gr_status)(struct gk20a *g);
void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
void (*set_alpha_circular_buffer_size)(struct gk20a *g,
u32 data);
void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
@@ -1193,8 +1192,7 @@ struct gops_gr {
u32 addr,
u32 max_offsets,
u32 *offsets, u32 *offset_addrs,
u32 *num_offsets,
bool is_quad, u32 quad);
u32 *num_offsets);
int (*process_context_buffer_priv_segment)(struct gk20a *g,
enum ctxsw_addr_type addr_type,
u32 pri_addr,