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1ff79b1d2c
quad type reg_ops were only needed on Kepler, and not for any other chip beginning Maxweel. HAL g->ops.gr.access_smpc_reg() was incorrectly set for Volta and Turing whereas it was only applicable to Kepler. Delete it. There is no register in the quad type whitelist since the type itself is not supported anymore. Remove the empty whitelists for all chips and also delete below HALs: g->ops.regops.get_qctl_whitelist() g->ops.regops.get_qctl_whitelist_count() hal/regops/regops_gv100.* files are not used anymore. Delete the files instead of just deleting quad HALs in these files. Bug 200628391 Change-Id: I4dcc04bef5c24eb4d63d913f492a8c00543163a2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2366035 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>