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gpu: nvgpu: move sema specific cmdbuf methods to common/sync/

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sema cmdbuf specific functions are only for the sync functionality
of nvgpu and do not belong to fifo.

construct files sema_cmdbuf_gk20a.h and sema_cmdbuf_gk20a.c
under common/sync to contain the syncpt specific cmdbuf functions
for arch gk20a.

Jira NVGPU-1308

Change-Id: Iebeebe7a3de627f2de08d4ced74bb1aabf1eb53c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975922
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Debarshi Dutta
2018-12-19 12:45:41 +05:30
committed by mobile promotions
parent 89c6bd2690
commit 20b15e6f40
9 changed files with 134 additions and 69 deletions
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83
drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.c Normal file
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/*
* GK20A sema cmdbuf
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/log.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/semaphore.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/channel.h>
#include "sema_cmdbuf_gk20a.h"
u32 gk20a_get_sema_wait_cmd_size(void)
{
return 8U;
}
u32 gk20a_get_sema_incr_cmd_size(void)
{
return 10U;
}
void gk20a_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s,
u64 sema_va, struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi)
{
nvgpu_log_fn(g, " ");
/* semaphore_a */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004U);
/* offset_upper */
nvgpu_mem_wr32(g, cmd->mem, off++, (u32)(sema_va >> 32) & 0xffU);
/* semaphore_b */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005U);
/* offset */
nvgpu_mem_wr32(g, cmd->mem, off++, (u32)sema_va & 0xffffffff);
if (acquire) {
/* semaphore_c */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
/* payload */
nvgpu_mem_wr32(g, cmd->mem, off++,
nvgpu_semaphore_get_value(s));
/* semaphore_d */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
/* operation: acq_geq, switch_en */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x4U | BIT32(12));
} else {
/* semaphore_c */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006U);
/* payload */
nvgpu_mem_wr32(g, cmd->mem, off++,
nvgpu_semaphore_get_value(s));
/* semaphore_d */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007U);
/* operation: release, wfi */
nvgpu_mem_wr32(g, cmd->mem, off++,
0x2UL | ((wfi ? 0x0UL : 0x1UL) << 20));
/* non_stall_int */
nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010008U);
/* ignored */
nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
}
}

37
drivers/gpu/nvgpu/common/sync/sema_cmdbuf_gk20a.h Normal file
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/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_SYNC_SEMA_CMDBUF_GK20A_H
#define NVGPU_SYNC_SEMA_CMDBUF_GK20A_H
#include <nvgpu/types.h>
struct gk20a;
struct priv_cmd_entry;
struct nvgpu_semaphore;
u32 gk20a_get_sema_wait_cmd_size(void);
u32 gk20a_get_sema_incr_cmd_size(void);
void gk20a_add_sema_cmd(struct gk20a *g, struct nvgpu_semaphore *s,
u64 sema_va, struct priv_cmd_entry *cmd,
u32 off, bool acquire, bool wfi);
#endif /* NVGPU_SYNC_SEMA_CMDBUF_GK20A_H */