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gpu: nvgpu: Change GPCPLL rev C1 control settings

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Updated DFS control settings for GPCPLL revision C1 per characterization
data.

Bug 1942222

Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1502741
(cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f)
Reviewed-on: https://git-master.nvidia.com/r/1525830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
This commit is contained in:
Alex Frid
2017-06-14 18:49:05 -07:00
committed by mobile promotions
parent 66ec347db4
commit 20d1b9a40d
2 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gk20a/clk_gk20a.h
View File

@@ -77,6 +77,8 @@ struct pll_parms {
u32 lock_timeout;
u32 na_lock_delay;
u32 iddq_exit_delay;
/* NA mode DFS control */
u32 dfs_ctrl;
};
struct namemap_cfg;

18
drivers/gpu/nvgpu/gm20b/clk_gm20b.c
View File

@@ -71,6 +71,7 @@ static struct pll_parms gpc_pll_params_c1 = {
500, /* Locking and ramping timeout */
40, /* Lock delay in NA mode */
5, /* IDDQ mode exit delay */
0x3 << 10, /* DFS control settings */
};
static struct pll_parms gpc_pll_params;
@@ -411,7 +412,7 @@ static void __maybe_unused clk_set_dfs_det_max(struct gk20a *g, u32 dfs_det_max)
static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal)
{
u32 data;
u32 data, ctrl;
data = gk20a_readl(g, trim_gpc_bcast_gpcpll_dvfs2_r());
data &= ~(BIT(DFS_DET_RANGE + 1) - 1);
@@ -420,10 +421,11 @@ static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal)
data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r());
nvgpu_udelay(1);
if (~trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data) & DFS_EXT_CAL_EN) {
ctrl = trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data);
if (~ctrl & DFS_EXT_CAL_EN) {
data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(),
trim_sys_gpcpll_dvfs1_dfs_ctrl_f(
DFS_EXT_CAL_EN | DFS_TESTOUT_DET));
trim_sys_gpcpll_dvfs1_dfs_ctrl_f(
ctrl | DFS_EXT_CAL_EN | DFS_TESTOUT_DET));
gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data);
}
}
@@ -472,6 +474,14 @@ static int clk_enbale_pll_dvfs(struct gk20a *g)
gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data);
}
/* Set NA mode DFS control */
if (p->dfs_ctrl) {
data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r());
data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(),
trim_sys_gpcpll_dvfs1_dfs_ctrl_f(p->dfs_ctrl));
gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data);
}
/*
* If calibration parameters are known (either from fuses, or from
* internal calibration on boot) - use them. Internal calibration is