nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: Reorg fifo HAL initialization

Browse Source 
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522553
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Sunny He
2017-06-30 15:53:08 -07:00
committed by mobile promotions
parent 2b582c5141
commit 66ec347db4
11 changed files with 238 additions and 117 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/gk20a/tsg_gk20a.c
View File

@@ -342,9 +342,3 @@ struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch)
return tsg;
}
void gk20a_init_tsg_ops(struct gpu_ops *gops)
{
gops->fifo.tsg_bind_channel = gk20a_tsg_bind_channel;
gops->fifo.tsg_unbind_channel = gk20a_tsg_unbind_channel;
}

2
drivers/gpu/nvgpu/gk20a/tsg_gk20a.h
View File

@@ -22,14 +22,12 @@
#define NVGPU_INVALID_TSG_ID (-1)
struct channel_gk20a;
struct gpu_ops;
bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch);
struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g);
void gk20a_tsg_release(struct kref *ref);
int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid);
void gk20a_init_tsg_ops(struct gpu_ops *gops);
struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch);
struct tsg_gk20a {

71
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -28,7 +28,7 @@
#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
#include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
static void channel_gm20b_bind(struct channel_gk20a *c)
void channel_gm20b_bind(struct channel_gk20a *c)
{
struct gk20a *g = c->g;
@@ -69,7 +69,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id)
return fault_id;
}
static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
unsigned long engine_ids)
{
unsigned long delay = GR_IDLE_CHECK_DEFAULT;
@@ -113,12 +113,12 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
}
static u32 gm20b_fifo_get_num_fifos(struct gk20a *g)
u32 gm20b_fifo_get_num_fifos(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}
static void gm20b_device_info_data_parse(struct gk20a *g,
void gm20b_device_info_data_parse(struct gk20a *g,
u32 table_entry, u32 *inst_id,
u32 *pri_base, u32 *fault_id)
{
@@ -139,7 +139,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g,
top_device_info_data_type_v(table_entry));
}
static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
{
/*
* These are all errors which indicate something really wrong
@@ -182,64 +182,3 @@ static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
f->intr.pbdma.restartable_0 =
pbdma_intr_0_device_pending_f();
}
void gm20b_init_fifo(struct gpu_ops *gops)
{
gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw;
gops->fifo.bind_channel = channel_gm20b_bind;
gops->fifo.unbind_channel = gk20a_fifo_channel_unbind;
gops->fifo.disable_channel = gk20a_fifo_disable_channel;
gops->fifo.enable_channel = gk20a_fifo_enable_channel;
gops->fifo.alloc_inst = gk20a_fifo_alloc_inst;
gops->fifo.free_inst = gk20a_fifo_free_inst;
gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc;
gops->fifo.channel_set_priority = gk20a_fifo_set_priority;
gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice;
gops->fifo.default_timeslice_us = gk20a_fifo_default_timeslice_us;
gops->fifo.setup_userd = gk20a_fifo_setup_userd;
gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get;
gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
gops->fifo.userd_pb_get = gk20a_fifo_userd_pb_get;
gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val;
gops->fifo.preempt_channel = gk20a_fifo_preempt_channel;
gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg;
gops->fifo.update_runlist = gk20a_fifo_update_runlist;
gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault;
gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info;
gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle;
gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos;
gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice;
gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
gops->fifo.device_info_data_parse = gm20b_device_info_data_parse;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.init_engine_info = gk20a_fifo_init_engine_info;
gops->fifo.runlist_entry_size = ram_rl_entry_size_v;
gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry;
gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry;
gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc;
gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status;
gops->fifo.dump_eng_status = gk20a_dump_eng_status;
gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc;
gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask;
gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending;
gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs;
gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0;
gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1;
#ifdef CONFIG_TEGRA_GK20A_NVHOST
gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf;
gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf;
gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd;
gops->fifo.get_syncpt_wait_cmd_size =
gk20a_fifo_get_syncpt_wait_cmd_size;
gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd;
gops->fifo.get_syncpt_incr_cmd_size =
gk20a_fifo_get_syncpt_incr_cmd_size;
#endif
}

12
drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
View File

@@ -1,7 +1,7 @@
/*
* GM20B Fifo
*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -17,5 +17,13 @@
#define _NVHOST_GM20B_FIFO
struct gk20a;
void gm20b_init_fifo(struct gpu_ops *gops);
void channel_gm20b_bind(struct channel_gk20a *c);
void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
unsigned long engine_ids);
u32 gm20b_fifo_get_num_fifos(struct gk20a *g);
void gm20b_device_info_data_parse(struct gk20a *g,
u32 table_entry, u32 *inst_id,
u32 *pri_base, u32 *fault_id);
void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
#endif

66
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -15,6 +15,7 @@
#include "gk20a/gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
#include "gk20a/fifo_gk20a.h"
#include "gk20a/css_gr_gk20a.h"
#include "gk20a/mc_gk20a.h"
#include "gk20a/bus_gk20a.h"
@@ -46,6 +47,9 @@
#include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
#define PRIV_SECURITY_DISABLE 0x01
@@ -202,6 +206,64 @@ static const struct gpu_ops gm20b_ops = {
.pg_gr_load_gating_prod =
gr_gm20b_pg_gr_load_gating_prod,
},
.fifo = {
.init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
.bind_channel = channel_gm20b_bind,
.unbind_channel = gk20a_fifo_channel_unbind,
.disable_channel = gk20a_fifo_disable_channel,
.enable_channel = gk20a_fifo_enable_channel,
.alloc_inst = gk20a_fifo_alloc_inst,
.free_inst = gk20a_fifo_free_inst,
.setup_ramfc = gk20a_fifo_setup_ramfc,
.channel_set_priority = gk20a_fifo_set_priority,
.channel_set_timeslice = gk20a_fifo_set_timeslice,
.default_timeslice_us = gk20a_fifo_default_timeslice_us,
.setup_userd = gk20a_fifo_setup_userd,
.userd_gp_get = gk20a_fifo_userd_gp_get,
.userd_gp_put = gk20a_fifo_userd_gp_put,
.userd_pb_get = gk20a_fifo_userd_pb_get,
.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
.preempt_channel = gk20a_fifo_preempt_channel,
.preempt_tsg = gk20a_fifo_preempt_tsg,
.update_runlist = gk20a_fifo_update_runlist,
.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
.wait_engine_idle = gk20a_fifo_wait_engine_idle,
.get_num_fifos = gm20b_fifo_get_num_fifos,
.get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
.device_info_data_parse = gm20b_device_info_data_parse,
.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
.init_engine_info = gk20a_fifo_init_engine_info,
.runlist_entry_size = ram_rl_entry_size_v,
.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
.dump_pbdma_status = gk20a_dump_pbdma_status,
.dump_eng_status = gk20a_dump_eng_status,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
.handle_sched_error = gk20a_fifo_handle_sched_error,
.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
.tsg_bind_channel = gk20a_tsg_bind_channel,
.tsg_unbind_channel = gk20a_tsg_unbind_channel,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
#endif
},
.mc = {
.intr_enable = mc_gk20a_intr_enable,
.intr_unit_config = mc_gk20a_intr_unit_config,
@@ -271,6 +333,7 @@ int gm20b_init_hal(struct gk20a *g)
gops->ltc = gm20b_ops.ltc;
gops->clock_gating = gm20b_ops.clock_gating;
gops->fifo = gm20b_ops.fifo;
gops->mc = gm20b_ops.mc;
gops->dbg_session_ops = gm20b_ops.dbg_session_ops;
gops->debug = gm20b_ops.debug;
@@ -320,7 +383,6 @@ int gm20b_init_hal(struct gk20a *g)
g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
gm20b_init_gr(gops);
gm20b_init_fb(gops);
gm20b_init_fifo(gops);
gm20b_init_ce2(gops);
gm20b_init_gr_ctx(gops);
gm20b_init_mm(gops);
@@ -328,7 +390,7 @@ int gm20b_init_hal(struct gk20a *g)
gm20b_init_clk_ops(gops);
gm20b_init_regops(gops);
gm20b_init_therm_ops(gops);
gk20a_init_tsg_ops(gops);
g->name = "gm20b";
c->twod_class = FERMI_TWOD_A;

11
drivers/gpu/nvgpu/gp106/fifo_gp106.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -19,14 +19,7 @@
#include <nvgpu/hw/gp106/hw_ccsr_gp106.h>
#include <nvgpu/hw/gp106/hw_fifo_gp106.h>
static u32 gp106_fifo_get_num_fifos(struct gk20a *g)
u32 gp106_fifo_get_num_fifos(struct gk20a *g)
{
return ccsr_channel__size_1_v();
}
void gp106_init_fifo(struct gpu_ops *gops)
{
gp10b_init_fifo(gops);
gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
}

6
drivers/gpu/nvgpu/gp106/fifo_gp106.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -13,6 +13,6 @@
#ifndef NVGPU_FIFO_GP106_H
#define NVGPU_FIFO_GP106_H
struct gpu_ops;
void gp106_init_fifo(struct gpu_ops *gops);
struct gk20a;
u32 gp106_fifo_get_num_fifos(struct gk20a *g);
#endif

68
drivers/gpu/nvgpu/gp106/hal_gp106.c
View File

@@ -14,6 +14,7 @@
*/
#include "gk20a/gk20a.h"
#include "gk20a/fifo_gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
#include "gk20a/css_gr_gk20a.h"
#include "gk20a/bus_gk20a.h"
@@ -31,6 +32,7 @@
#include "gp10b/regops_gp10b.h"
#include "gp10b/cde_gp10b.h"
#include "gp10b/priv_ring_gp10b.h"
#include "gp10b/fifo_gp10b.h"
#include "gp106/fifo_gp106.h"
#include "gp106/regops_gp106.h"
@@ -62,6 +64,9 @@
#include <nvgpu/bus.h>
#include <nvgpu/hw/gp106/hw_proj_gp106.h>
#include <nvgpu/hw/gp106/hw_fifo_gp106.h>
#include <nvgpu/hw/gp106/hw_ram_gp106.h>
#include <nvgpu/hw/gp106/hw_top_gp106.h>
static int gp106_get_litter_value(struct gk20a *g, int value)
{
@@ -243,6 +248,66 @@ static const struct gpu_ops gp106_ops = {
.pg_gr_load_gating_prod =
gr_gp106_pg_gr_load_gating_prod,
},
.fifo = {
.init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
.bind_channel = channel_gm20b_bind,
.unbind_channel = gk20a_fifo_channel_unbind,
.disable_channel = gk20a_fifo_disable_channel,
.enable_channel = gk20a_fifo_enable_channel,
.alloc_inst = gk20a_fifo_alloc_inst,
.free_inst = gk20a_fifo_free_inst,
.setup_ramfc = channel_gp10b_setup_ramfc,
.channel_set_priority = gk20a_fifo_set_priority,
.channel_set_timeslice = gk20a_fifo_set_timeslice,
.default_timeslice_us = gk20a_fifo_default_timeslice_us,
.setup_userd = gk20a_fifo_setup_userd,
.userd_gp_get = gk20a_fifo_userd_gp_get,
.userd_gp_put = gk20a_fifo_userd_gp_put,
.userd_pb_get = gk20a_fifo_userd_pb_get,
.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
.preempt_channel = gk20a_fifo_preempt_channel,
.preempt_tsg = gk20a_fifo_preempt_tsg,
.update_runlist = gk20a_fifo_update_runlist,
.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
.wait_engine_idle = gk20a_fifo_wait_engine_idle,
.get_num_fifos = gp106_fifo_get_num_fifos,
.get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
.device_info_data_parse = gp10b_device_info_data_parse,
.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
.init_engine_info = gk20a_fifo_init_engine_info,
.runlist_entry_size = ram_rl_entry_size_v,
.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
.dump_pbdma_status = gk20a_dump_pbdma_status,
.dump_eng_status = gk20a_dump_eng_status,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
.handle_sched_error = gk20a_fifo_handle_sched_error,
.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
.tsg_bind_channel = gk20a_tsg_bind_channel,
.tsg_unbind_channel = gk20a_tsg_unbind_channel,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
#endif
.resetup_ramfc = gp10b_fifo_resetup_ramfc,
.device_info_fault_id = top_device_info_data_fault_id_enum_v,
},
.mc = {
.intr_enable = mc_gp10b_intr_enable,
.intr_unit_config = mc_gp10b_intr_unit_config,
@@ -331,6 +396,7 @@ int gp106_init_hal(struct gk20a *g)
gops->ltc = gp106_ops.ltc;
gops->clock_gating = gp106_ops.clock_gating;
gops->fifo = gp106_ops.fifo;
gops->mc = gp106_ops.mc;
gops->debug = gp106_ops.debug;
gops->dbg_session_ops = gp106_ops.dbg_session_ops;
@@ -358,7 +424,6 @@ int gp106_init_hal(struct gk20a *g)
gp106_init_gr(gops);
gp10b_init_fecs_trace_ops(gops);
gp106_init_fb(gops);
gp106_init_fifo(gops);
gp10b_init_ce(gops);
gp106_init_gr_ctx(gops);
gp106_init_mm(gops);
@@ -366,7 +431,6 @@ int gp106_init_hal(struct gk20a *g)
gp106_init_clk_ops(gops);
gp106_init_clk_arb_ops(gops);
gp106_init_regops(gops);
gk20a_init_tsg_ops(gops);
gk20a_init_pramin_ops(gops);
gp106_init_therm_ops(gops);

28
drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
View File

@@ -80,7 +80,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c)
return 0;
}
static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
u64 gpfifo_base, u32 gpfifo_entries,
unsigned long acquire_timeout, u32 flags)
{
@@ -147,13 +147,13 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
return channel_gp10b_commit_userd(c);
}
static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g)
{
return g->gpu_characteristics.gpfifo_class
| pbdma_signature_sw_zero_f();
}
static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
{
u32 new_syncpt = 0, old_syncpt;
u32 v;
@@ -192,7 +192,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c)
return 0;
}
static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
u32 *inst_id)
{
int ret = ENGINE_INVAL_GK20A;
@@ -208,7 +208,7 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
return ret;
}
static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
u32 *inst_id, u32 *pri_base, u32 *fault_id)
{
if (top_device_info_data_type_v(table_entry) ==
@@ -232,7 +232,7 @@ static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
top_device_info_data_type_v(table_entry));
}
static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
{
/*
* These are all errors which indicate something really wrong
@@ -277,7 +277,7 @@ static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
pbdma_intr_0_device_pending_f();
}
static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
struct mmu_fault_info *mmfault)
{
u32 fault_info;
@@ -307,17 +307,3 @@ static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
/* note: inst_ptr is a 40b phys addr. */
mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v();
}
void gp10b_init_fifo(struct gpu_ops *gops)
{
gm20b_init_fifo(gops);
gops->fifo.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info;
gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc;
gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature;
gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc;
gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type;
gops->fifo.device_info_data_parse = gp10b_device_info_data_parse;
gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v;
gops->fifo.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs;
}

17
drivers/gpu/nvgpu/gp10b/fifo_gp10b.h
View File

@@ -1,7 +1,7 @@
/*
* GP10B Fifo
*
* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -18,8 +18,21 @@
struct gpu_ops;
struct channel_gk20a;
struct fifo_gk20a;
struct mmu_fault_info;
void gp10b_init_fifo(struct gpu_ops *gops);
int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
u64 gpfifo_base, u32 gpfifo_entries,
unsigned long acquire_timeout, u32 flags);
u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g);
int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c);
int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type,
u32 *inst_id);
void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry,
u32 *inst_id, u32 *pri_base, u32 *fault_id);
void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
struct mmu_fault_info *mmfault);
int channel_gp10b_commit_userd(struct channel_gk20a *c);
#endif

68
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -14,6 +14,7 @@
*/
#include "gk20a/gk20a.h"
#include "gk20a/fifo_gk20a.h"
#include "gk20a/dbg_gpu_gk20a.h"
#include "gk20a/css_gr_gk20a.h"
#include "gk20a/bus_gk20a.h"
@@ -43,6 +44,7 @@
#include "gm20b/fifo_gm20b.h"
#include "gm20b/pmu_gm20b.h"
#include "gm20b/clk_gm20b.h"
#include "gm20b/fifo_gm20b.h"
#include "gp10b.h"
#include "hal_gp10b.h"
@@ -54,6 +56,9 @@
#include <nvgpu/hw/gp10b/hw_proj_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
static int gp10b_get_litter_value(struct gk20a *g, int value)
{
@@ -210,6 +215,66 @@ static const struct gpu_ops gp10b_ops = {
.pg_gr_load_gating_prod =
gr_gp10b_pg_gr_load_gating_prod,
},
.fifo = {
.init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
.bind_channel = channel_gm20b_bind,
.unbind_channel = gk20a_fifo_channel_unbind,
.disable_channel = gk20a_fifo_disable_channel,
.enable_channel = gk20a_fifo_enable_channel,
.alloc_inst = gk20a_fifo_alloc_inst,
.free_inst = gk20a_fifo_free_inst,
.setup_ramfc = channel_gp10b_setup_ramfc,
.channel_set_priority = gk20a_fifo_set_priority,
.channel_set_timeslice = gk20a_fifo_set_timeslice,
.default_timeslice_us = gk20a_fifo_default_timeslice_us,
.setup_userd = gk20a_fifo_setup_userd,
.userd_gp_get = gk20a_fifo_userd_gp_get,
.userd_gp_put = gk20a_fifo_userd_gp_put,
.userd_pb_get = gk20a_fifo_userd_pb_get,
.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
.preempt_channel = gk20a_fifo_preempt_channel,
.preempt_tsg = gk20a_fifo_preempt_tsg,
.update_runlist = gk20a_fifo_update_runlist,
.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
.wait_engine_idle = gk20a_fifo_wait_engine_idle,
.get_num_fifos = gm20b_fifo_get_num_fifos,
.get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
.set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
.force_reset_ch = gk20a_fifo_force_reset_ch,
.engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
.device_info_data_parse = gp10b_device_info_data_parse,
.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
.init_engine_info = gk20a_fifo_init_engine_info,
.runlist_entry_size = ram_rl_entry_size_v,
.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
.get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
.dump_pbdma_status = gk20a_dump_pbdma_status,
.dump_eng_status = gk20a_dump_eng_status,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
.handle_sched_error = gk20a_fifo_handle_sched_error,
.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
.tsg_bind_channel = gk20a_tsg_bind_channel,
.tsg_unbind_channel = gk20a_tsg_unbind_channel,
#ifdef CONFIG_TEGRA_GK20A_NVHOST
.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
#endif
.resetup_ramfc = gp10b_fifo_resetup_ramfc,
.device_info_fault_id = top_device_info_data_fault_id_enum_v,
},
.mc = {
.intr_enable = mc_gp10b_intr_enable,
.intr_unit_config = mc_gp10b_intr_unit_config,
@@ -281,6 +346,7 @@ int gp10b_init_hal(struct gk20a *g)
gops->ltc = gp10b_ops.ltc;
gops->clock_gating = gp10b_ops.clock_gating;
gops->fifo = gp10b_ops.fifo;
gops->mc = gp10b_ops.mc;
gops->debug = gp10b_ops.debug;
gops->dbg_session_ops = gp10b_ops.dbg_session_ops;
@@ -340,14 +406,12 @@ int gp10b_init_hal(struct gk20a *g)
gp10b_init_gr(gops);
gp10b_init_fecs_trace_ops(gops);
gp10b_init_fb(gops);
gp10b_init_fifo(gops);
gp10b_init_ce(gops);
gp10b_init_gr_ctx(gops);
gp10b_init_mm(gops);
gp10b_init_pmu_ops(gops);
gp10b_init_regops(gops);
gp10b_init_therm_ops(gops);
gk20a_init_tsg_ops(gops);
gk20a_init_pramin_ops(gops);
g->name = "gp10b";