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gpu: nvgpu: support nvgpu-next intr config

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JIRA NVGPU-4864

Change-Id: I2fb5be3270c73ea891021161f539a7f731e05f63
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2314372
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Seema Khowala
2020-03-17 19:17:52 -07:00
committed by Alex Waterman
parent a5b3170c6f
commit 21e2214c3d
2 changed files with 48 additions and 0 deletions
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42
drivers/gpu/nvgpu/common/mc/mc.c
View File

@@ -24,6 +24,7 @@
#include <nvgpu/mc.h> #include <nvgpu/mc.h>
#include <nvgpu/gk20a.h> #include <nvgpu/gk20a.h>
#include <nvgpu/bug.h>
void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
{ {
@@ -122,3 +123,44 @@ void nvgpu_mc_intr_nonstall_resume(struct gk20a *g)
g->ops.mc.intr_nonstall_resume(g); g->ops.mc.intr_nonstall_resume(g);
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags); nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
} }
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit,
u32 *vectorid, u32 num_entries)
{
unsigned long flags = 0;
u32 i = 0U;
struct nvgpu_intr_unit_info *intr_unit_info;
nvgpu_assert(num_entries <= INTR_VECTORID_SIZE_MAX);
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == false) {
for (i = 0U; i < num_entries; i++) {
intr_unit_info[unit].vectorid[i] = *(vectorid + i);
}
intr_unit_info[unit].vectorid_size = num_entries;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
}
bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit)
{
unsigned long flags = 0;
struct nvgpu_intr_unit_info *intr_unit_info;
bool info_valid = false;
intr_unit_info = g->mc.nvgpu_next.intr_unit_info;
nvgpu_spinlock_irqsave(&g->mc.intr_lock, flags);
if (intr_unit_info[unit].valid == true) {
info_valid = true;
}
nvgpu_spinunlock_irqrestore(&g->mc.intr_lock, flags);
return info_valid;
}
#endif

6
drivers/gpu/nvgpu/include/nvgpu/mc.h
View File

@@ -501,4 +501,10 @@ void nvgpu_mc_intr_nonstall_pause(struct gk20a *g);
*/ */
void nvgpu_mc_intr_nonstall_resume(struct gk20a *g); void nvgpu_mc_intr_nonstall_resume(struct gk20a *g);
#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
void nvgpu_mc_intr_unit_vectorid_init(struct gk20a *g, u32 unit,
u32 *vectorid, u32 num_entries);
bool nvgpu_mc_intr_is_unit_info_valid(struct gk20a *g, u32 unit);
#endif
#endif #endif