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gpu: nvgpu: disable unused compute sw method in safety build.

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NVC0C0_SET_SHADER_EXCEPTIONS is never used by CUDA software. Hence disable that
feature with CONFIG_NVGPU_HAL_NON_FUSA checking for safety build.

Jira NVGPU-4454

Change-Id: If71b97bf8b2a6a8f8d0c7206b8e801094b5b1b7c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256345
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
2019-12-05 13:01:01 -08:00
committed by Alex Waterman
parent 76adb91f60
commit 22dea4ca3b
3 changed files with 24 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b.h
View File

@@ -65,7 +65,6 @@ void gv11b_gr_intr_set_shader_cut_collector(struct gk20a *g, u32 data);
void gv11b_gr_intr_set_skedcheck(struct gk20a *g, u32 data);
int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
u32 gpc_exception,
u32 *corrected_err, u32 *uncorrected_err);
@@ -110,6 +109,10 @@ u64 gv11b_gr_intr_get_sm_hww_warp_esr_pc(struct gk20a *g, u32 offset);
u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
#endif
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
void gv11b_gr_intr_set_tex_in_dbg(struct gk20a *g, u32 data);
#endif

32
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gv11b_fusa.c
View File

@@ -155,9 +155,11 @@ int gv11b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
if (class_num == VOLTA_COMPUTE_A) {
switch (offset << 2) {
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
case NVC0C0_SET_SHADER_EXCEPTIONS:
g->ops.gr.intr.set_shader_exceptions(g, data);
break;
#endif
case NVC3C0_SET_SKEDCHECK:
gv11b_gr_intr_set_skedcheck(g, data);
break;
@@ -218,20 +220,6 @@ fail:
return ret;
}
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
{
nvgpu_log_fn(g, " ");
if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) {
nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
0);
nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(),
0);
} else {
g->ops.gr.intr.set_hww_esr_report_mask(g);
}
}
void gv11b_gr_intr_handle_gcc_exception(struct gk20a *g, u32 gpc,
u32 gpc_exception,
u32 *corrected_err, u32 *uncorrected_err)
@@ -1747,6 +1735,22 @@ u32 gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val(void)
return gr_fecs_ctxsw_mailbox_value_ctxsw_checksum_mismatch_v();
}
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gv11b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data)
{
nvgpu_log_fn(g, " ");
if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) {
nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(),
0);
nvgpu_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(),
0);
} else {
g->ops.gr.intr.set_hww_esr_report_mask(g);
}
}
#endif
#if defined(CONFIG_NVGPU_DEBUGGER) && defined(CONFIG_NVGPU_GRAPHICS)
void gv11b_gr_intr_set_tex_in_dbg(struct gk20a *g, u32 data)
{

4
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -628,8 +628,6 @@ static const struct gpu_ops gv11b_ops = {
.intr = {
.handle_fecs_error = gv11b_gr_intr_handle_fecs_error,
.handle_sw_method = gv11b_gr_intr_handle_sw_method,
.set_shader_exceptions =
gv11b_gr_intr_set_shader_exceptions,
.handle_class_error =
gm20b_gr_intr_handle_class_error,
.clear_pending_interrupts =
@@ -701,6 +699,8 @@ static const struct gpu_ops gv11b_ops = {
.get_ctxsw_checksum_mismatch_mailbox_val =
gv11b_gr_intr_ctxsw_checksum_mismatch_mailbox_val,
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
.set_shader_exceptions =
gv11b_gr_intr_set_shader_exceptions,
.tpc_exception_sm_enable =
gm20b_gr_intr_tpc_exception_sm_enable,
#endif