gpu: nvgpu: modify pbdma.get_fc_target

Modify pbdma.get_fc_target() to accept nvgpu_device pointer. This is
required for nvgpu-next.

JIRA NVGPU-6135

Change-Id: I8baa58c704ee32ee68e87915029ac2be2132d4a4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2440180
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -30,6 +30,7 @@ struct nvgpu_debug_context;
 struct nvgpu_channel_dump_info;
 struct nvgpu_gpfifo_entry;
 struct nvgpu_pbdma_status_info;
+struct nvgpu_device;
 
 bool gm20b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id,
 			u32 pbdma_intr_0, u32 *error_notifier);
@@ -55,7 +56,7 @@ u32 gm20b_pbdma_get_gp_base(u64 gpfifo_base);
 u32 gm20b_pbdma_get_gp_base_hi(u64 gpfifo_base, u32 gpfifo_entry);
 
 u32 gm20b_pbdma_get_fc_subdevice(void);
-u32 gm20b_pbdma_get_fc_target(void);
+u32 gm20b_pbdma_get_fc_target(const struct nvgpu_device *dev);
 u32 gm20b_pbdma_get_ctrl_hce_priv_mode_yes(void);
 u32 gm20b_pbdma_get_userd_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem);
 u32 gm20b_pbdma_get_userd_addr(u32 addr_lo);

drivers/gpu/nvgpu/hal/fifo/pbdma_gm20b_fusa.c

@@ -35,6 +35,7 @@
 #include <nvgpu/pbdma_status.h>
 #include <nvgpu/static_analysis.h>
 #include <nvgpu/rc.h>
+#include <nvgpu/device.h>
 
 #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h>
 
@@ -385,7 +386,7 @@ u32 gm20b_pbdma_get_fc_subdevice(void)
 		pbdma_subdevice_channel_dma_enable_f());
 }
 
-u32 gm20b_pbdma_get_fc_target(void)
+u32 gm20b_pbdma_get_fc_target(const struct nvgpu_device *dev)
 {
 	return pbdma_target_engine_sw_f();
 }

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b.h

@@ -26,6 +26,7 @@
 #include <nvgpu/types.h>
 
 struct gk20a;
+struct nvgpu_device;
 
 void gv11b_pbdma_setup_hw(struct gk20a *g);
 void gv11b_pbdma_intr_enable(struct gk20a *g, bool enable);
@@ -35,7 +36,7 @@ bool gv11b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
 			u32 *error_notifier);
 u32 gv11b_pbdma_channel_fatal_0_intr_descs(void);
 u32 gv11b_pbdma_get_fc_pb_header(void);
-u32 gv11b_pbdma_get_fc_target(void);
+u32 gv11b_pbdma_get_fc_target(const struct nvgpu_device *dev);
 u32 gv11b_pbdma_set_channel_info_veid(u32 subctx_id);
 u32 gv11b_pbdma_config_userd_writeback_enable(u32 v);
 

drivers/gpu/nvgpu/hal/fifo/pbdma_gv11b_fusa.c

@@ -26,6 +26,7 @@
 #include <nvgpu/fifo.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/soc.h>
+#include <nvgpu/device.h>
 
 #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h>
 
@@ -263,9 +264,9 @@ u32 gv11b_pbdma_get_fc_pb_header(void)
 		pbdma_pb_header_type_inc_f());
 }
 
-u32 gv11b_pbdma_get_fc_target(void)
+u32 gv11b_pbdma_get_fc_target(const struct nvgpu_device *dev)
 {
-	return (gm20b_pbdma_get_fc_target() |
+	return (gm20b_pbdma_get_fc_target(dev) |
 			pbdma_target_eng_ctx_valid_true_f() |
 			pbdma_target_ce_ctx_valid_true_f());
 }

drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -86,7 +86,7 @@ int gk20a_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
 		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		g->ops.pbdma.get_fc_target());
+		g->ops.pbdma.get_fc_target(NULL));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));

drivers/gpu/nvgpu/hal/fifo/ramfc_gp10b.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -62,7 +62,7 @@ int gp10b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
 		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		g->ops.pbdma.get_fc_target());
+		g->ops.pbdma.get_fc_target(NULL));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));

drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b_fusa.c

@@ -72,7 +72,7 @@ int gv11b_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
 		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		g->ops.pbdma.get_fc_target());
+		g->ops.pbdma.get_fc_target(NULL));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));

drivers/gpu/nvgpu/hal/fifo/ramfc_tu104.c

@@ -60,7 +60,7 @@ int tu104_ramfc_setup(struct nvgpu_channel *ch, u64 gpfifo_base,
 		g->ops.pbdma.get_fc_subdevice());
 
 	nvgpu_mem_wr32(g, mem, ram_fc_target_w(),
-		g->ops.pbdma.get_fc_target());
+		g->ops.pbdma.get_fc_target(NULL));
 
 	nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(),
 		g->ops.pbdma.acquire_val(pbdma_acquire_timeout));

drivers/gpu/nvgpu/include/nvgpu/gops/pbdma.h

@@ -27,6 +27,7 @@
 struct gk20a;
 struct nvgpu_gpfifo_entry;
 struct nvgpu_pbdma_status_info;
+struct nvgpu_device;
 
 /** @cond DOXYGEN_SHOULD_SKIP_THIS */
 
@@ -68,7 +69,7 @@ struct gops_pbdma {
 	u32 (*get_fc_formats)(void);
 	u32 (*get_fc_pb_header)(void);
 	u32 (*get_fc_subdevice)(void);
-	u32 (*get_fc_target)(void);
+	u32 (*get_fc_target)(const struct nvgpu_device *dev);
 	u32 (*get_ctrl_hce_priv_mode_yes)(void);
 	u32 (*get_userd_aperture_mask)(struct gk20a *g,
 			struct nvgpu_mem *mem);

userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.c

@@ -338,7 +338,7 @@ int test_gv11b_pbdma_get_fc(struct unit_module *m,
 		 pbdma_pb_header_first_true_f() |
 		 pbdma_pb_header_type_inc_f()), goto done);
 
-	unit_assert(gv11b_pbdma_get_fc_target() ==
+	unit_assert(gv11b_pbdma_get_fc_target(NULL) ==
 		(pbdma_target_engine_sw_f() |
 		 pbdma_target_eng_ctx_valid_true_f() |
 		 pbdma_target_ce_ctx_valid_true_f()), goto done);

userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.c

@@ -89,7 +89,7 @@ static u32 stub_pbdma_get_fc_subdevice(void)
 	return 0U;
 }
 
-static u32 stub_pbdma_get_fc_target(void)
+static u32 stub_pbdma_get_fc_target(const struct nvgpu_device *dev)
 {
 	global_count++;
 	return 0U;