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gpu: nvgpu: gp10b: Add SM debug registers

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Add SM debug registers to gp10b, and regenerate headers.

Bug 1567274

Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/592646
This commit is contained in:
Terje Bergstrom
2014-11-03 10:37:29 +02:00
committed by Deepak Nibade
parent 1e4861a347
commit 23a4456260
3 changed files with 67 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h
View File

@@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void)
}
static inline u32 gmmu_pte_comptagline_f(u32 v)
{
return (v & 0x1ffff) << 12;
return (v & 0x3ffff) << 12;
}
static inline u32 gmmu_pte_comptagline_w(void)
{

64
drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
View File

@@ -2814,6 +2814,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
{
return 0x40000000;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
{
return 0x0050460c;
@@ -2826,6 +2834,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
{
return 0x00000001;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
{
return 0x00419e50;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
{
return 0x10;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
{
return 0x20;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
{
return 0x40;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
{
return 0x00504650;
@@ -3226,4 +3250,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
{
return 0x004188ac;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
{
return 0x00419e10;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
{
return (v & 0x1) << 0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
{
return 0x00000001;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
{
return 0x1 << 31;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
{
return (r >> 31) & 0x1;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
{
return 0x1 << 30;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
{
return (r >> 30) & 0x1;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
{
return 0x40000000;
}
#endif

4
drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h
View File

@@ -124,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
return (v & 0x3ffff) << 0;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
{
@@ -132,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
{
return (v & 0x1ffff) << 0;
return (v & 0x3ffff) << 0;
}
static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
{