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gpu: nvgpu: split ecc_gv11b fusa/non-fusa hal

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functions in ecc_gv11b.c are needed in ecc_gv11b_fusa.c, hence moved
them there. Updated the arch yaml to reflect the fusa and non-fusa
units for ecc.

JIRA NVGPU-3690

Change-Id: Id7b65901840a1f9494215f722cdcb943e243aaa4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156876
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-07-19 10:39:34 +05:30
committed by mobile promotions
parent ccef4f9c56
commit 249ffa0fb0
5 changed files with 79 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
arch/nvgpu-hal-new.yaml
View File

@@ -379,15 +379,16 @@ gr:
safe: yes
owner: Deepak N
children:
ecc:
ecc_fusa:
safe: yes
sources: [hal/gr/ecc/ecc_gv11b_fusa.c,
hal/gr/ecc/ecc_gv11b.h ]
ecc:
safe: no
sources: [hal/gr/ecc/ecc_gp10b.c,
hal/gr/ecc/ecc_gv11b.c,
hal/gr/ecc/ecc_gv11b_fusa.c,
hal/gr/ecc/ecc_tu104.c,
hal/gr/ecc/ecc_gp10b.h,
hal/gr/ecc/ecc_gv11b.h,
hal/gr/ecc/ecc_tu104.h]
hal/gr/ecc/ecc_tu104.h ]
ctxsw_prog:
safe: yes
sources: [ hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c,

1
drivers/gpu/nvgpu/Makefile
View File

@@ -191,7 +191,6 @@ nvgpu-y += \
hal/clk/clk_gm20b.o \
hal/clk/clk_gv100.o \
hal/gr/ecc/ecc_gp10b.o \
hal/gr/ecc/ecc_gv11b.o \
hal/gr/ecc/ecc_tu104.o \
hal/gr/zcull/zcull_gm20b.o \
hal/gr/zcull/zcull_gv11b.o \

1
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -145,7 +145,6 @@ srcs += common/utils/enabled.c \
common/fifo/pbdma_status.c \
common/fifo/userd.c \
common/mc/mc.c \
hal/gr/ecc/ecc_gv11b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gp10b.c \
hal/gr/ctxsw_prog/ctxsw_prog_gv11b.c \

102
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b.c
View File

@@ -1,102 +0,0 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include <nvgpu/io.h>
#include <nvgpu/ecc.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
#include "ecc_gv11b.h"
int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting FECS fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int tpc_stride =
nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFF00U) >> 8U;
unsigned int tpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_add_u32(
nvgpu_safe_mult_u32(gpc , gpc_stride),
nvgpu_safe_mult_u32(tpc , tpc_stride)));
nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d",
err->name, gpc, tpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g,
GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}

73
drivers/gpu/nvgpu/hal/gr/ecc/ecc_gv11b_fusa.c
View File

@@ -28,6 +28,79 @@
#include "ecc_gv11b.h"
int gv11b_gr_intr_inject_fecs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting FECS fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gpccs_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GPCCS fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_sm_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err,
u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int tpc_stride =
nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFF00U) >> 8U;
unsigned int tpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_add_u32(
nvgpu_safe_mult_u32(gpc , gpc_stride),
nvgpu_safe_mult_u32(tpc , tpc_stride)));
nvgpu_info(g, "Injecting SM fault %s for gpc: %d, tpc: %d",
err->name, gpc, tpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_mmu_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting MMU fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
int gv11b_gr_intr_inject_gcc_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
unsigned int gpc_stride = nvgpu_get_litter_value(g,
GPU_LIT_GPC_STRIDE);
unsigned int gpc = (error_info & 0xFFU);
unsigned int reg_addr = nvgpu_safe_add_u32(err->get_reg_addr(),
nvgpu_safe_mult_u32(gpc , gpc_stride));
nvgpu_info(g, "Injecting GCC fault %s for gpc: %d", err->name, gpc);
nvgpu_writel(g, reg_addr, err->get_reg_val(1U));
return 0;
}
static inline u32 fecs_falcon_ecc_control_r(void)
{
return gr_fecs_falcon_ecc_control_r();