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gpu: nvgpu: split pmu_gv11b fusa/non-fusa hal

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gv11b_pmu_inject_ecc_error is needed in fusa functions. Hence moved it
to pmu_gv11b_fusa.c. Moved compilation of pmu_gv11b.c under NON_FUSA
and updated the arch.

JIRA NVGPU-3690

Change-Id: I88488591a72b8e43eccba44fc2afe4d0b5973a1c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156875
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-07-19 10:23:48 +05:30
committed by mobile promotions
parent bda3f066e7
commit ccef4f9c56
4 changed files with 20 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/nvgpu-hal-new.yaml
View File

@@ -536,21 +536,25 @@ fb:
hal/fb/intr/fb_intr_ecc_gv11b_fusa.c,
hal/fb/intr/fb_intr_tu104.c, hal/fb/intr/fb_intr_tu104.h ]
pmu:
pmu_fusa:
safe: yes
owner: Mahantesh K
sources: [ hal/pmu/pmu_gp106_fusa.c,
hal/pmu/pmu_gp106.h,
hal/pmu/pmu_gv11b_fusa.c,
hal/pmu/pmu_gv11b.h ]
pmu:
safe: no
owner: Mahantesh K
sources: [ hal/pmu/pmu_gk20a.c,
hal/pmu/pmu_gk20a.h,
hal/pmu/pmu_gm20b.c,
hal/pmu/pmu_gm20b.h,
hal/pmu/pmu_gp106.c,
hal/pmu/pmu_gp106_fusa.c,
hal/pmu/pmu_gp106.h,
hal/pmu/pmu_gp10b.c,
hal/pmu/pmu_gp10b.h,
hal/pmu/pmu_gv11b.c,
hal/pmu/pmu_gv11b_fusa.c,
hal/pmu/pmu_gv11b.h,
hal/pmu/pmu_tu104.c,
hal/pmu/pmu_tu104.h ]

4
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -165,8 +165,7 @@ srcs += common/utils/enabled.c \
hal/fifo/pbdma_gp10b.c \
hal/fifo/userd_gk20a.c \
hal/fifo/mmu_fault_gp10b.c \
hal/sync/syncpt_cmdbuf_gv11b.c \
hal/pmu/pmu_gv11b.c
hal/sync/syncpt_cmdbuf_gv11b.c
# Source files below are functionaly safe (FuSa) and must always be included.
srcs += hal/mm/mm_gv11b_fusa.c \
@@ -314,6 +313,7 @@ srcs += hal/init/hal_gp10b.c \
hal/netlist/netlist_gp10b.c \
hal/sync/syncpt_cmdbuf_gk20a.c \
hal/pmu/pmu_gp106.c \
hal/pmu/pmu_gv11b.c \
hal/top/top_gm20b.c \
hal/top/top_gp106.c
endif

9
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
View File

@@ -39,15 +39,6 @@
#define ALIGN_4KB 12
int gv11b_pmu_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting PMU fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
#ifdef CONFIG_NVGPU_LS_PMU
/* PROD settings for ELPG sequencing registers*/
static struct pg_init_sequence_list _pginitseq_gv11b[] = {

9
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b_fusa.c
View File

@@ -39,6 +39,15 @@
#define ALIGN_4KB 12
int gv11b_pmu_inject_ecc_error(struct gk20a *g,
struct nvgpu_hw_err_inject_info *err, u32 error_info)
{
nvgpu_info(g, "Injecting PMU fault %s", err->name);
nvgpu_writel(g, err->get_reg_addr(), err->get_reg_val(1U));
return 0;
}
static inline u32 pmu_falcon_ecc_control_r(void)
{
return pwr_pmu_falcon_ecc_control_r();