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gpu: nvgpu: set ACR FW load flag as per platform

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-Add ACR FW load flag which will be set based on
 platform and load the requested FW accordingly.

Bug 3572869

Change-Id: I6643f183fed104fef059dd691036a2c509073a50
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2689022
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Andy Chiang <achiang@nvidia.com>
This commit is contained in:
mkumbar
2022-03-29 12:47:09 +05:30
committed by mobile promotions
parent 1ce899ce46
commit 2506dd2b86
4 changed files with 40 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/gpu/nvgpu/common/acr/acr.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -172,6 +172,21 @@ int nvgpu_acr_init(struct gk20a *g)
break; break;
} }
/*
* Firmware is stored in soc specific path in FMODEL
* Hence NVGPU_REQUEST_FIRMWARE_NO_WARN is used instead
* of NVGPU_REQUEST_FIRMWARE_NO_SOC
*/
if (err == 0) {
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
g->acr->fw_load_flag = NVGPU_REQUEST_FIRMWARE_NO_WARN;
} else
#endif
{
g->acr->fw_load_flag = NVGPU_REQUEST_FIRMWARE_NO_SOC;
}
}
done: done:
return err; return err;
} }

32
drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
View File

@@ -182,29 +182,29 @@ int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
switch (ver) { switch (ver) {
case NVGPU_GPUID_GV11B: case NVGPU_GPUID_GV11B:
fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
break; break;
case NVGPU_GPUID_GA10B: case NVGPU_GPUID_GA10B:
if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) { if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
fecs_sig = nvgpu_request_firmware(g, fecs_sig = nvgpu_request_firmware(g,
GM20B_FECS_UCODE_SIG, GM20B_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
} else { } else {
fecs_sig = nvgpu_request_firmware(g, fecs_sig = nvgpu_request_firmware(g,
GA10B_FECS_UCODE_PKC_SIG, GA10B_FECS_UCODE_PKC_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
} }
break; break;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104: case NVGPU_GPUID_TU104:
fecs_sig = nvgpu_request_firmware(g, TU104_FECS_UCODE_SIG, fecs_sig = nvgpu_request_firmware(g, TU104_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
break; break;
#endif #endif
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
case NVGPU_GPUID_GA100: case NVGPU_GPUID_GA100:
fecs_sig = nvgpu_request_firmware(g, GA100_FECS_UCODE_SIG, fecs_sig = nvgpu_request_firmware(g, GA100_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
break; break;
#endif #endif
@@ -325,29 +325,29 @@ int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
switch (ver) { switch (ver) {
case NVGPU_GPUID_GV11B: case NVGPU_GPUID_GV11B:
gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
break; break;
case NVGPU_GPUID_GA10B: case NVGPU_GPUID_GA10B:
if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) { if (!nvgpu_is_enabled(g, NVGPU_PKC_LS_SIG_ENABLED)) {
gpccs_sig = nvgpu_request_firmware(g, gpccs_sig = nvgpu_request_firmware(g,
T18x_GPCCS_UCODE_SIG, T18x_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
} else { } else {
gpccs_sig = nvgpu_request_firmware(g, gpccs_sig = nvgpu_request_firmware(g,
GA10B_GPCCS_UCODE_PKC_SIG, GA10B_GPCCS_UCODE_PKC_SIG,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
} }
break; break;
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104: case NVGPU_GPUID_TU104:
gpccs_sig = nvgpu_request_firmware(g, TU104_GPCCS_UCODE_SIG, gpccs_sig = nvgpu_request_firmware(g, TU104_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
break; break;
#endif #endif
#if defined(CONFIG_NVGPU_NON_FUSA) #if defined(CONFIG_NVGPU_NON_FUSA)
case NVGPU_GPUID_GA100: case NVGPU_GPUID_GA100:
gpccs_sig = nvgpu_request_firmware(g, GA100_GPCCS_UCODE_SIG, gpccs_sig = nvgpu_request_firmware(g, GA100_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
break; break;
#endif #endif
@@ -469,11 +469,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img)
if (g->is_fusa_sku) { if (g->is_fusa_sku) {
sec2_fw = nvgpu_request_firmware(g, sec2_fw = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_IMAGE_FUSA_BIN, LSF_SEC2_UCODE_IMAGE_FUSA_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} else { } else {
sec2_fw = nvgpu_request_firmware(g, sec2_fw = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_IMAGE_BIN, LSF_SEC2_UCODE_IMAGE_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} }
if (sec2_fw == NULL) { if (sec2_fw == NULL) {
@@ -487,11 +487,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img)
if (g->is_fusa_sku) { if (g->is_fusa_sku) {
sec2_desc = nvgpu_request_firmware(g, sec2_desc = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_DESC_FUSA_BIN, LSF_SEC2_UCODE_DESC_FUSA_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} else { } else {
sec2_desc = nvgpu_request_firmware(g, sec2_desc = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_DESC_BIN, LSF_SEC2_UCODE_DESC_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} }
if (sec2_desc == NULL) { if (sec2_desc == NULL) {
@@ -505,11 +505,11 @@ int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img)
if (g->is_fusa_sku) { if (g->is_fusa_sku) {
sec2_sig = nvgpu_request_firmware(g, sec2_sig = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_SIG_FUSA_BIN, LSF_SEC2_UCODE_SIG_FUSA_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} else { } else {
sec2_sig = nvgpu_request_firmware(g, sec2_sig = nvgpu_request_firmware(g,
LSF_SEC2_UCODE_SIG_BIN, LSF_SEC2_UCODE_SIG_BIN,
NVGPU_REQUEST_FIRMWARE_NO_SOC); g->acr->fw_load_flag);
} }
if (sec2_sig == NULL) { if (sec2_sig == NULL) {
nvgpu_err(g, "failed to load SEC2 sig!!"); nvgpu_err(g, "failed to load SEC2 sig!!");

22
drivers/gpu/nvgpu/common/acr/acr_bootstrap.c
View File

@@ -246,22 +246,10 @@ int nvgpu_acr_bootstrap_hs_ucode(struct gk20a *g, struct nvgpu_acr *acr,
return err; return err;
} }
} else { } else {
/* Firmware is stored in soc specific path in FMODEL
* Hence NVGPU_REQUEST_FIRMWARE_NO_WARN is used instead
* of NVGPU_REQUEST_FIRMWARE_NO_SOC
*/
#ifdef CONFIG_NVGPU_SIM
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
acr_fw = nvgpu_request_firmware(g, acr_fw = nvgpu_request_firmware(g,
acr_desc->acr_fw_name, acr_desc->acr_fw_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
} else
#endif
{
acr_fw = nvgpu_request_firmware(g,
acr_desc->acr_fw_name,
NVGPU_REQUEST_FIRMWARE_NO_SOC);
}
if (acr_fw == NULL) { if (acr_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s", nvgpu_err(g, "%s ucode get fail for %s",
acr_desc->acr_fw_name, g->name); acr_desc->acr_fw_name, g->name);
@@ -334,7 +322,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
nvgpu_acr_dbg(g, "loading ACR's manifest bin\n"); nvgpu_acr_dbg(g, "loading ACR's manifest bin\n");
acr->manifest_fw = nvgpu_request_firmware(g, acr->manifest_fw = nvgpu_request_firmware(g,
acr->acr_manifest_name, acr->acr_manifest_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
if (acr->manifest_fw == NULL) { if (acr->manifest_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s", nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_manifest_name, g->name); acr->acr_manifest_name, g->name);
@@ -344,7 +332,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
nvgpu_acr_dbg(g, "loading ACR's text bin\n"); nvgpu_acr_dbg(g, "loading ACR's text bin\n");
acr->code_fw = nvgpu_request_firmware(g, acr->code_fw = nvgpu_request_firmware(g,
acr->acr_code_name, acr->acr_code_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
if (acr->code_fw == NULL) { if (acr->code_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s", nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_code_name, g->name); acr->acr_code_name, g->name);
@@ -355,7 +343,7 @@ static int ga10b_load_riscv_acr_ucodes(struct gk20a *g, struct hs_acr *acr)
nvgpu_acr_dbg(g, "loading ACR's data bin\n"); nvgpu_acr_dbg(g, "loading ACR's data bin\n");
acr->data_fw = nvgpu_request_firmware(g, acr->data_fw = nvgpu_request_firmware(g,
acr->acr_data_name, acr->acr_data_name,
NVGPU_REQUEST_FIRMWARE_NO_WARN); g->acr->fw_load_flag);
if (acr->data_fw == NULL) { if (acr->data_fw == NULL) {
nvgpu_err(g, "%s ucode get fail for %s", nvgpu_err(g, "%s ucode get fail for %s",
acr->acr_data_name, g->name); acr->acr_data_name, g->name);

1
drivers/gpu/nvgpu/common/acr/acr_priv.h
View File

@@ -130,6 +130,7 @@ struct acr_lsf_config {
struct nvgpu_acr { struct nvgpu_acr {
struct gk20a *g; struct gk20a *g;
u32 fw_load_flag;
u32 bootstrap_owner; u32 bootstrap_owner;
u32 num_of_sig; u32 num_of_sig;