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gpu: nvgpu: unit: update 'Targets' for fifo units

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This patch adds a number of missing 'Targets' fields in the SWUTS of
various fifo units, fixes some missing ones and adds gops based
targets.

Jira NVGPU-4376

Change-Id: I445196e7092b01853786f40b860b29abc5d68371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2020-01-08 17:02:27 -05:00
committed by Alex Waterman
parent b7be2379c0
commit 2540a98aa4
27 changed files with 186 additions and 93 deletions
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29
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.h
View File

@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_acquire_val
* Targets: gops_pbdma.acquire_val, gm20b_pbdma_acquire_val
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -66,7 +66,7 @@ int test_gm20b_pbdma_acquire_val(struct unit_module *m,
*
* Description: Branch coverage for PBDMA interrupt handler
*
* Targets: gm20b_pbdma_handle_intr
* Targets: gops_pbdma.handle_intr, gm20b_pbdma_handle_intr
*
* Test Type: Feature
*
@@ -98,7 +98,8 @@ int test_gm20b_pbdma_handle_intr(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_handle_intr_0, gm20b_pbdma_reset_header
* Targets: gops_pbdma.handle_intr_0, gm20b_pbdma_handle_intr_0,
* gops_pbdma.reset_header, gm20b_pbdma_reset_header
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -133,7 +134,7 @@ int test_gm20b_pbdma_handle_intr_0(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_read_data
* Targets: gops_pbdma.read_data, gm20b_pbdma_read_data
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -154,7 +155,9 @@ int test_gm20b_pbdma_read_data(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_device_fatal_0_intr_descs,
* Targets: gops_pbdma.device_fatal_0_intr_descs,
* gm20b_pbdma_device_fatal_0_intr_descs,
* gops_pbdma.restartable_0_intr_descs
* gm20b_pbdma_restartable_0_intr_descs.
*
* Input: test_fifo_init_support() run for this GPU
@@ -177,7 +180,7 @@ int test_gm20b_pbdma_intr_descs(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_format_gpfifo_entry
* Targets: gops_pbdma.format_gpfifo_entry, gm20b_pbdma_format_gpfifo_entry
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -199,7 +202,8 @@ int test_gm20b_pbdma_format_gpfifo_entry(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_gp_base, test_gm20b_pbdma_get_gp_base_hi
* Targets: gops_pbdma.get_gp_base, gm20b_pbdma_get_gp_base,
* gops_pbdma.get_gp_base_hi, gm20b_pbdma_get_gp_base_hi
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -223,7 +227,7 @@ int test_gm20b_pbdma_get_gp_base(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_fc_subdevice
* Targets: gops_pbdma.get_fc_subdevice, gm20b_pbdma_get_fc_subdevice
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -243,7 +247,8 @@ int test_gm20b_pbdma_get_fc_subdevice(struct unit_module *m,
*
* Test Type: Feature based
*
* Targets: gm20b_pbdma_get_ctrl_hce_priv_mode_yes
* Targets: gops_pbdma.get_ctrl_hce_priv_mode_yes,
* gm20b_pbdma_get_ctrl_hce_priv_mode_yes
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -263,8 +268,10 @@ int test_gm20b_pbdma_get_ctrl_hce_priv_mode_yes(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_userd_addr, gm20b_pbdma_get_userd_hi_addr,
* gm20b_pbdma_get_userd_aperture_mask
* Targets: gops_pbdma.get_userd_addr, gm20b_pbdma_get_userd_addr,
* gops_pbdma.get_userd_hi_addr, gm20b_pbdma_get_userd_hi_addr,
* gops_pbdma.get_userd_aperture_mask,
* gm20b_pbdma_get_userd_aperture_mask
*
* Input: test_fifo_init_support() run for this GPU
*

22
userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_setup_hw
* Targets: gops_pbdma.setup_hw, gv11b_pbdma_setup_hw
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -61,7 +61,7 @@ int test_gv11b_pbdma_setup_hw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: test_gv11b_pbdma_intr_enable
* Targets: gops_pbdma.intr_enable, gv11b_pbdma_intr_enable
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -96,7 +96,7 @@ int test_gv11b_pbdma_intr_enable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_handle_intr_0
* Targets: gops_pbdma.handle_intr_0, gv11b_pbdma_handle_intr_0
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -121,7 +121,7 @@ int test_gv11b_pbdma_handle_intr_0(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_handle_intr_1
* Targets: gops_pbdma.handle_intr_1, gv11b_pbdma_handle_intr_1
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -145,7 +145,8 @@ int test_gv11b_pbdma_handle_intr_1(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_channel_fatal_0_intr_descs.
* Targets: gops_pbdma.channel_fatal_0_intr_descs,
* gv11b_pbdma_channel_fatal_0_intr_descs
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -165,7 +166,8 @@ int test_gv11b_pbdma_intr_descs(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_get_fc_pb_header, gv11b_pbdma_get_fc_target
* Targets: gops_pbdma.get_fc_pb_header, gv11b_pbdma_get_fc_pb_header,
* gops_pbdma.get_fc_target, gv11b_pbdma_get_fc_target
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -187,7 +189,8 @@ int test_gv11b_pbdma_get_fc(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_set_channel_info_veid
* Targets: gops_pbdma.set_channel_info_veid,
* gv11b_pbdma_set_channel_info_veid
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -207,7 +210,8 @@ int test_gv11b_pbdma_set_channel_info_veid(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_config_userd_writeback_enable
* Targets: gops_pbdma.config_userd_writeback_enable
* gv11b_pbdma_config_userd_writeback_enable
*
* Input: test_fifo_init_support() run for this GPU
*

11
userspace/units/fifo/pbdma/nvgpu-pbdma.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_setup_sw, nvgpu_pbdma_cleanup_sw
*
* Input: none.
*
* Steps:
@@ -66,6 +68,8 @@ int test_pbdma_setup_sw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_find_for_runlist, nvgpu_engine_is_valid_runlist_id
*
* Input: test_fifo_init_support() run for this GPU.
*
* Steps:
@@ -88,6 +92,11 @@ int test_pbdma_find_for_runlist(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_status_is_chsw_switch, nvgpu_pbdma_status_is_chsw_load,
* nvgpu_pbdma_status_is_chsw_save, nvgpu_pbdma_status_is_chsw_valid,
* nvgpu_pbdma_status_is_id_type_tsg,
* nvgpu_pbdma_status_is_next_id_type_tsg
*
* Input: test_fifo_init_support() run for this GPU.
*
* Steps: