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gpu: nvgpu: unit: update 'Targets' for fifo units

Browse Source 
This patch adds a number of missing 'Targets' fields in the SWUTS of
various fifo units, fixes some missing ones and adds gops based
targets.

Jira NVGPU-4376

Change-Id: I445196e7092b01853786f40b860b29abc5d68371
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2276680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2020-01-08 17:02:27 -05:00
committed by Alex Waterman
parent b7be2379c0
commit 2540a98aa4
27 changed files with 186 additions and 93 deletions
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10
userspace/units/fifo/channel/gk20a/nvgpu-channel-gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_channel.enable, gk20a_channel_enable
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -59,6 +61,8 @@ int test_gk20a_channel_enable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.disable, gk20a_channel_disable
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -78,6 +82,8 @@ int test_gk20a_channel_disable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.read_state, gk20a_channel_read_state
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -85,7 +91,7 @@ int test_gk20a_channel_disable(struct unit_module *m,
* - Build ccsr_channel_r with all combinations of next, enable,
* status and busy fields.
* - Check that interpreted status for next, enabled, busy, ctx_reload
* and pending_acquire are in accordaance with fields read from H/W.
* and pending_acquire are in accordance with fields read from H/W.
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/

9
userspace/units/fifo/channel/gm20b/nvgpu-channel-gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gm20b_channel_bind
* Targets: gops_channel.bind, gm20b_channel_bind
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -59,8 +59,6 @@ struct gk20a;
int test_gm20b_channel_bind(struct unit_module *m,
struct gk20a *g, void *args);
/**
* Test specification for: test_gm20b_channel_force_ctx_reload
*
@@ -68,7 +66,7 @@ int test_gm20b_channel_bind(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_channel_force_ctx_reload
* Targets: gops_channel.force_ctx_reload, gm20b_channel_force_ctx_reload
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -85,7 +83,6 @@ int test_gm20b_channel_bind(struct unit_module *m,
int test_gm20b_channel_force_ctx_reload(struct unit_module *m,
struct gk20a *g, void *args);
/**
* @}
*/

12
userspace/units/fifo/channel/gv11b/nvgpu-channel-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_channel.unbind, gv11b_channel_unbind
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -63,6 +65,8 @@ int test_gv11b_channel_unbind(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.count, gv11b_channel_count
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -80,6 +84,8 @@ int test_gv11b_channel_count(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.read_state, gv11b_channel_read_state
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -102,6 +108,8 @@ int test_gv11b_channel_read_state(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.reset_faulted, gv11b_channel_reset_faulted
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -123,6 +131,8 @@ int test_gv11b_channel_reset_faulted(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_channel.debug_dump, gv11b_channel_debug_dump
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

7
userspace/units/fifo/ctxsw_timeout/gv11b/nvgpu-ctxsw-timeout-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature based
*
* Targets: gv11b_fifo_ctxsw_timeout_enable
* Targets: gops_fifo.ctxsw_timeout_enable, gv11b_fifo_ctxsw_timeout_enable
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -61,7 +61,8 @@ int test_gv11b_fifo_ctxsw_timeout_enable(struct unit_module *m,
*
* Test Type: Feature based
*
* Targets: gv11b_fifo_handle_ctxsw_timeout, gv11b_fifo_ctxsw_timeout_info
* Targets: gops_fifo.handle_ctxsw_timeout, gv11b_fifo_handle_ctxsw_timeout,
* gops_fifo.ctxsw_timeout_info, gv11b_fifo_ctxsw_timeout_info
*
* Input: test_fifo_init_support() run for this GPU
*

5
userspace/units/fifo/engine/gm20b/nvgpu-engine-gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,9 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_engine_status.read_engine_status_info,
* gm20b_read_engine_status_info
*
* Input: test_fifo_init_support has run.
*
* Steps:

4
userspace/units/fifo/engine/gp10b/nvgpu-engine-gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gp10b_engine_init_ce_info
*
* Input: test_fifo_init_support has run..
*
* Steps:

7
userspace/units/fifo/engine/gv100/nvgpu-engine-gv100.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,9 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_engine_status.read_engine_status_info,
* gv100_read_engine_status_info
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -59,6 +62,8 @@ int test_gv100_read_engine_status_info(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_engine_status.dump_engine_status, gv100_dump_engine_status
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

5
userspace/units/fifo/engine/gv11b/nvgpu-engine-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,9 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_engine.is_fault_engine_subid_gpc,
* gv11b_is_fault_engine_subid_gpc
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

36
userspace/units/fifo/engine/nvgpu-engine.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -36,20 +36,24 @@ struct gk20a;
*/
/**
* Test specification for: test_engines_setup_sw
* Test specification for: test_engine_setup_sw
*
* Description: Branch coverage for nvgpu_channel_setup/cleanup_sw.
* Description: Branch coverage for nvgpu_engine_setup/cleanup_sw.
*
* Test Type: Feature
*
* Targets: nvgpu_engine_setup_sw, nvgpu_engine_cleanup_sw
*
* Input: None
*
* Steps:
* - Check valid case for nvgpu_channel_setup_sw.
* - Check valid case for nvgpu_channel_cleanup_sw.
* - Check invalid case for nvgpu_channel_setup_sw.
* - Failure to allocate channel contexts (by using fault injection for
* vzalloc).
* - Check valid case for nvgpu_engine_setup_sw.
* - Check valid case for nvgpu_engine_cleanup_sw.
* - Check invalid case for nvgpu_engine_setup_sw.
* - Failure to allocate engine contexts (w/ fault injection)
* - Failure to allocate active engines list (w/ fault injection)
* - Failure to initialize engine info (using stub for
* g->ops.engine.init_info)
*
* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
*/
@@ -63,6 +67,8 @@ int test_engine_setup_sw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_engine_init_info
*
* Input: test_fifo_init_support must have run.
*
* Steps:
@@ -82,12 +88,13 @@ int test_engine_init_info(struct unit_module *m,
/**
* Test specification for: test_engine_ids
*
* Description: Branch coverage for nvgpu_engine_get_ids,
* nvgpu_engine_check_valid_id and
* nvgpu_engine_get_gr_id
* Description: Branch coverage for engine ids
*
* Test Type: Feature
*
* Targets: nvgpu_engine_get_ids, nvgpu_engine_check_valid_id,
* nvgpu_engine_get_gr_id
*
* Input: test_fifo_init_support must have run.
*
* Steps:
@@ -112,6 +119,8 @@ int test_engine_ids(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_engine_get_active_eng_info, nvgpu_engine_check_valid_id
*
* Input: test_engine_ids must have run.
*
* Steps:
@@ -134,6 +143,8 @@ int test_engine_get_active_eng_info(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_engine_enum_from_type
*
* Input: test_engine_ids must have run.
*
* Steps:
@@ -178,9 +189,6 @@ int test_engine_enum_from_type(struct unit_module *m,
int test_engine_interrupt_mask(struct unit_module *m,
struct gk20a *g, void *args);
/**
* @}
*/

7
userspace/units/fifo/fifo/gk20a/nvgpu-fifo-gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gk20a_fifo_init_pbdma_map
* Targets: gops_fifo.init_pbdma_map, gk20a_fifo_init_pbdma_map
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -62,7 +62,8 @@ int test_gk20a_init_pbdma_map(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gk20a_fifo_get_runlist_timeslice, gk20a_fifo_get_pb_timeslice
* Targets: gops_fifo.get_runlist_timeslice, gk20a_fifo_get_runlist_timeslice,
* gops_fifo.get_pb_timeslice, gk20a_fifo_get_pb_timeslice
*
* Input: test_fifo_init_support() run for this GPU
*

14
userspace/units/fifo/fifo/gk20a/nvgpu-fifo-intr-gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gk20a_fifo_intr_1_enable
* Targets: gops_fifo.intr_1_enable, gk20a_fifo_intr_1_enable
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -63,7 +63,7 @@ int test_gk20a_fifo_intr_1_enable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gk20a_fifo_intr_1_isr
* Targets: gops_fifo.intr_1_isr, gk20a_fifo_intr_1_isr
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -85,7 +85,8 @@ int test_gk20a_fifo_intr_1_isr(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gk20a_fifo_intr_handle_chsw_error
* Targets: gops_fifo.intr_handle_chsw_error,
* gk20a_fifo_intr_handle_chsw_error
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -110,7 +111,8 @@ int test_gk20a_fifo_intr_handle_chsw_error(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gk20a_fifo_intr_handle_runlist_event
* Targets: gops_fifo.intr_handle_runlist_event,
* gk20a_fifo_intr_handle_runlist_event
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -133,7 +135,7 @@ int test_gk20a_fifo_intr_handle_runlist_event(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gk20a_fifo_pbdma_isr
* Targets: gk20a_fifo_pbdma_isr, gops_fifo.pbdma_isr
*
* Input: test_fifo_init_support() run for this GPU
*

8
userspace/units/fifo/fifo/gv11b/nvgpu-fifo-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gv11b_init_fifo_reset_enable_hw, gv11b_init_fifo_setup_hw
* Targets: gops_fifo.reset_enable_hw, gv11b_init_fifo_reset_enable_hw,
* gops_fifo.init_fifo_setup_hw, gv11b_init_fifo_setup_hw
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -63,7 +64,8 @@ int test_gv11b_fifo_init_hw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_fifo_mmu_fault_id_to_pbdma_id
* Targets: gops_fifo.mmu_fault_id_to_pbdma_id,
* gv11b_fifo_mmu_fault_id_to_pbdma_id
*
* Input: test_fifo_init_support() run for this GPU
*

13
userspace/units/fifo/fifo/gv11b/nvgpu-fifo-intr-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gv11b_fifo_intr_0_enable
* Targets: gops_fifo.intr_0_enable, gv11b_fifo_intr_0_enable
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -69,7 +69,7 @@ int test_gv11b_fifo_intr_0_enable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_fifo_handle_sched_error
* Targets: gops_fifo.handle_sched_error, gv11b_fifo_handle_sched_error
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -92,7 +92,7 @@ int test_gv11b_fifo_handle_sched_error(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_fifo_intr_0_isr
* Targets: gops_fifo.intr_0_isr, gv11b_fifo_intr_0_isr
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -118,7 +118,10 @@ int test_gv11b_fifo_intr_0_isr(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_fifo_intr_set_recover_mask, gv11b_fifo_intr_unset_recover_mask
* Targets: gops_fifo.intr_set_recover_mask,
* gv11b_fifo_intr_set_recover_mask,
* gops_fifo.intr_unset_recover_mask,
* gv11b_fifo_intr_unset_recover_mask
*
* Input: test_fifo_init_support() run for this GPU
*

7
userspace/units/fifo/nvgpu-fifo-common.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -48,6 +48,8 @@
*
* Test Type: Feature
*
* Targets: nvgpu_fifo_init_support, nvgpu_fifo_cleanup_sw_common
*
* Input: None
*
* Steps:
@@ -79,6 +81,9 @@ int test_fifo_init_support(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_fifo_remove_support, nvgpu_fifo_cleanup_sw,
* nvgpu_fifo_cleanup_sw_common
*
* Input: test_fifo_init_support() called for this GPU.
*
* Steps:

29
userspace/units/fifo/pbdma/gm20b/nvgpu-pbdma-gm20b.h
View File

@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_acquire_val
* Targets: gops_pbdma.acquire_val, gm20b_pbdma_acquire_val
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -66,7 +66,7 @@ int test_gm20b_pbdma_acquire_val(struct unit_module *m,
*
* Description: Branch coverage for PBDMA interrupt handler
*
* Targets: gm20b_pbdma_handle_intr
* Targets: gops_pbdma.handle_intr, gm20b_pbdma_handle_intr
*
* Test Type: Feature
*
@@ -98,7 +98,8 @@ int test_gm20b_pbdma_handle_intr(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_handle_intr_0, gm20b_pbdma_reset_header
* Targets: gops_pbdma.handle_intr_0, gm20b_pbdma_handle_intr_0,
* gops_pbdma.reset_header, gm20b_pbdma_reset_header
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -133,7 +134,7 @@ int test_gm20b_pbdma_handle_intr_0(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_read_data
* Targets: gops_pbdma.read_data, gm20b_pbdma_read_data
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -154,7 +155,9 @@ int test_gm20b_pbdma_read_data(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_device_fatal_0_intr_descs,
* Targets: gops_pbdma.device_fatal_0_intr_descs,
* gm20b_pbdma_device_fatal_0_intr_descs,
* gops_pbdma.restartable_0_intr_descs
* gm20b_pbdma_restartable_0_intr_descs.
*
* Input: test_fifo_init_support() run for this GPU
@@ -177,7 +180,7 @@ int test_gm20b_pbdma_intr_descs(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_format_gpfifo_entry
* Targets: gops_pbdma.format_gpfifo_entry, gm20b_pbdma_format_gpfifo_entry
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -199,7 +202,8 @@ int test_gm20b_pbdma_format_gpfifo_entry(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_gp_base, test_gm20b_pbdma_get_gp_base_hi
* Targets: gops_pbdma.get_gp_base, gm20b_pbdma_get_gp_base,
* gops_pbdma.get_gp_base_hi, gm20b_pbdma_get_gp_base_hi
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -223,7 +227,7 @@ int test_gm20b_pbdma_get_gp_base(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_fc_subdevice
* Targets: gops_pbdma.get_fc_subdevice, gm20b_pbdma_get_fc_subdevice
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -243,7 +247,8 @@ int test_gm20b_pbdma_get_fc_subdevice(struct unit_module *m,
*
* Test Type: Feature based
*
* Targets: gm20b_pbdma_get_ctrl_hce_priv_mode_yes
* Targets: gops_pbdma.get_ctrl_hce_priv_mode_yes,
* gm20b_pbdma_get_ctrl_hce_priv_mode_yes
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -263,8 +268,10 @@ int test_gm20b_pbdma_get_ctrl_hce_priv_mode_yes(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gm20b_pbdma_get_userd_addr, gm20b_pbdma_get_userd_hi_addr,
* gm20b_pbdma_get_userd_aperture_mask
* Targets: gops_pbdma.get_userd_addr, gm20b_pbdma_get_userd_addr,
* gops_pbdma.get_userd_hi_addr, gm20b_pbdma_get_userd_hi_addr,
* gops_pbdma.get_userd_aperture_mask,
* gm20b_pbdma_get_userd_aperture_mask
*
* Input: test_fifo_init_support() run for this GPU
*

22
userspace/units/fifo/pbdma/gv11b/nvgpu-pbdma-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_setup_hw
* Targets: gops_pbdma.setup_hw, gv11b_pbdma_setup_hw
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -61,7 +61,7 @@ int test_gv11b_pbdma_setup_hw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: test_gv11b_pbdma_intr_enable
* Targets: gops_pbdma.intr_enable, gv11b_pbdma_intr_enable
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -96,7 +96,7 @@ int test_gv11b_pbdma_intr_enable(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_handle_intr_0
* Targets: gops_pbdma.handle_intr_0, gv11b_pbdma_handle_intr_0
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -121,7 +121,7 @@ int test_gv11b_pbdma_handle_intr_0(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_handle_intr_1
* Targets: gops_pbdma.handle_intr_1, gv11b_pbdma_handle_intr_1
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -145,7 +145,8 @@ int test_gv11b_pbdma_handle_intr_1(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_channel_fatal_0_intr_descs.
* Targets: gops_pbdma.channel_fatal_0_intr_descs,
* gv11b_pbdma_channel_fatal_0_intr_descs
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -165,7 +166,8 @@ int test_gv11b_pbdma_intr_descs(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_get_fc_pb_header, gv11b_pbdma_get_fc_target
* Targets: gops_pbdma.get_fc_pb_header, gv11b_pbdma_get_fc_pb_header,
* gops_pbdma.get_fc_target, gv11b_pbdma_get_fc_target
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -187,7 +189,8 @@ int test_gv11b_pbdma_get_fc(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_set_channel_info_veid
* Targets: gops_pbdma.set_channel_info_veid,
* gv11b_pbdma_set_channel_info_veid
*
* Input: test_fifo_init_support() run for this GPU
*
@@ -207,7 +210,8 @@ int test_gv11b_pbdma_set_channel_info_veid(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gv11b_pbdma_config_userd_writeback_enable
* Targets: gops_pbdma.config_userd_writeback_enable
* gv11b_pbdma_config_userd_writeback_enable
*
* Input: test_fifo_init_support() run for this GPU
*

11
userspace/units/fifo/pbdma/nvgpu-pbdma.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_setup_sw, nvgpu_pbdma_cleanup_sw
*
* Input: none.
*
* Steps:
@@ -66,6 +68,8 @@ int test_pbdma_setup_sw(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_find_for_runlist, nvgpu_engine_is_valid_runlist_id
*
* Input: test_fifo_init_support() run for this GPU.
*
* Steps:
@@ -88,6 +92,11 @@ int test_pbdma_find_for_runlist(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: nvgpu_pbdma_status_is_chsw_switch, nvgpu_pbdma_status_is_chsw_load,
* nvgpu_pbdma_status_is_chsw_save, nvgpu_pbdma_status_is_chsw_valid,
* nvgpu_pbdma_status_is_id_type_tsg,
* nvgpu_pbdma_status_is_next_id_type_tsg
*
* Input: test_fifo_init_support() run for this GPU.
*
* Steps:

6
userspace/units/fifo/ramfc/gv11b/nvgpu-ramfc-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature based
*
* Targets: gv11b_ramfc_setup
* Targets: gops_ramfc.setup, gv11b_ramfc_setup
*
* Input: None
*
@@ -59,7 +59,7 @@ int test_gv11b_ramfc_setup(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature based
*
* Targets: gv11b_ramfc_capture_ram_dump
* Targets: gops_ramfc.capture_ram_dump, gv11b_ramfc_capture_ram_dump
*
* Input: None
*

6
userspace/units/fifo/ramin/gk20a/ramin-gk20a-fusa.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature based
*
* Targets: gk20a_ramin_base_shift
* Targets: gops_ramin.base_shift, gk20a_ramin_base_shift
*
* Input: None
*
@@ -61,7 +61,7 @@ int test_gk20a_ramin_base_shift(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature based
*
* Targets: gk20a_ramin_alloc_size
* Targets: gops_ramin.alloc_size, gk20a_ramin_alloc_size
*
* Input: None
*

4
userspace/units/fifo/ramin/gm20b/ramin-gm20b-fusa.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature based
*
* Targets: gm20b_ramin_set_big_page_size
* Targets: gops_ramin.set_big_page_size, gm20b_ramin_set_big_page_size
*
* Input: None
*

6
userspace/units/fifo/ramin/gp10b/ramin-gp10b-fusa.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,13 +34,13 @@ struct gk20a;
*/
/**
* Test specification for: test_gv11b_ramin_set_gr_ptr
* Test specification for: test_gp10b_ramin_set_gr_ptr
*
* Description: Initialize instance block's PDB
*
* Test Type: Feature based
*
* Targets: gv11b_ramin_set_gr_ptr
* Targets: gops_ramin.set_gr_ptr, gp10b_ramin_set_gr_ptr
*
* Input: None
*

10
userspace/units/fifo/ramin/gv11b/ramin-gv11b-fusa.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature based
*
* Targets: gv11b_ramin_set_gr_ptr
* Targets: gops_ramin.set_gr_ptr, gv11b_ramin_set_gr_ptr
*
* Input: None
*
@@ -61,8 +61,8 @@ int test_gv11b_ramin_set_gr_ptr(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature based
*
* Targets: gv11b_ramin_init_subctx_pdb, gv11b_subctx_commit_pdb,
* gv11b_subctx_commit_valid_mask
* Targets: gops_ramin.init_subctx_pdb, gv11b_ramin_init_subctx_pdb,
* gv11b_subctx_commit_pdb, gv11b_subctx_commit_valid_mask
*
* Input: None
*
@@ -85,7 +85,7 @@ int test_gv11b_ramin_init_subctx_pdb(struct unit_module *m, struct gk20a *g,
*
* Test Type: Feature based
*
* Targets: gv11b_ramin_set_eng_method_buffer
* Targets: gops_ramin.set_eng_method_buffer, gv11b_ramin_set_eng_method_buffer
*
* Input: None
*

10
userspace/units/fifo/runlist/gk20a/nvgpu-runlist-gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_runlist.length_max, gk20a_runlist_length_max
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -57,6 +59,8 @@ int test_gk20a_runlist_length_max(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_runlist.hw_submit, gk20a_runlist_hw_submit
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -76,6 +80,8 @@ int test_gk20a_runlist_hw_submit(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_runlist.wait_pending, gk20a_runlist_wait_pending
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -106,6 +112,8 @@ int test_gk20a_runlist_wait_pending(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_runlist.write_state, gk20a_runlist_write_state
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

8
userspace/units/fifo/runlist/gv11b/nvgpu-runlist-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,8 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_runlist.entry_size, gv11b_runlist_entry_size
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -57,6 +59,8 @@ int test_gv11b_runlist_entry_size(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_runlist.get_tsg_entry, gv11b_runlist_get_tsg_entry
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -79,6 +83,8 @@ int test_gv11b_runlist_get_tsg_entry(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_runlist.get_ch_entry, gv11b_runlist_get_ch_entry
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

11
userspace/units/fifo/tsg/gv11b/nvgpu-tsg-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,6 +40,9 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gops_tsg.init_eng_method_buffers,
* gv11b_tsg_init_eng_method_buffers
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -73,6 +76,9 @@ int test_gv11b_tsg_init_eng_method_buffers(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_tsg.bind_channel_eng_method_buffers,
* gv11b_tsg_bind_channel_eng_method_buffers
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:
@@ -100,6 +106,9 @@ int test_gv11b_tsg_bind_channel_eng_method_buffers(struct unit_module *m,
*
* Test Type: Feature
*
* Targets: gops_tsg.unbind_channel_check_eng_faulted
* gv11b_tsg_unbind_channel_check_eng_faulted
*
* Input: test_fifo_init_support() run for this GPU
*
* Steps:

4
userspace/units/fifo/userd/gk20a/nvgpu-userd-gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gk20a_userd_entry_size
* Targets: gops_userd.entry_size, gk20a_userd_entry_size
*
* Input: test_fifo_init_support() run for this GPU
*

8
userspace/units/fifo/usermode/gv11b/nvgpu-usermode-gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -40,8 +40,10 @@ struct gk20a;
*
* Test Type: Feature
*
* Targets: gv11b_usermode_base, gv11b_usermode_bus_base,
* gv11b_usermode_doorbell_token, gv11b_usermode_ring_doorbell
* Targets: gops_usermode.base, gv11b_usermode_base,
* gops_usermode.bus_base, gv11b_usermode_bus_base,
* gops_usermode.doorbell_token, gv11b_usermode_doorbell_token,
* gops_usermode.ring_doorbell, gv11b_usermode_ring_doorbell
*
* Input: test_fifo_init_support() run for this GPU
*