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gpu: nvgpu: pmu: cast assignments of sizeof to u32

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This change fixes a number of This is a MISRA 10.3 rule violation due to
the implicit casts of sizeof() to u32's. This change adds u32 casts to
each of these violations. This should be safe because a 4GB type size
would be very unlikely in this driver.

JIRA NVGPU-1008

Change-Id: Icb6dd719b167fd48b86d89837897f1501fd24794
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959429
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2018-11-27 11:01:46 -05:00
committed by mobile promotions
parent d740a9cec6
commit 2558fca236
6 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/common/pmu/pmu.c
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@@ -385,7 +385,7 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
}
nvgpu_falcon_copy_from_dmem(pmu->flcn, tail + PMU_MSG_HDR_SIZE,
(u8 *)&msg->msg, msg->hdr.size - PMU_MSG_HDR_SIZE, 0);
(u8 *)&msg->msg, (u32)msg->hdr.size - PMU_MSG_HDR_SIZE, 0);
if (msg->msg.init.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) {
nvgpu_err(g, "expecting init msg");
@@ -402,7 +402,7 @@ int nvgpu_pmu_process_init_msg(struct nvgpu_pmu *pmu,
nvgpu_falcon_copy_from_dmem(pmu->flcn,
pv->get_pmu_init_msg_pmu_sw_mg_off(init),
(u8 *)&gid_data,
sizeof(struct pmu_sha1_gid_data), 0);
(u32)sizeof(struct pmu_sha1_gid_data), 0);
pmu->gid_info.valid =
(*gid_hdr_data == PMU_SHA1_GID_SIGNATURE);

2
drivers/gpu/nvgpu/common/pmu/pmu_debug.c
View File

@@ -36,7 +36,7 @@ void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu)
nvgpu_err(g, "Print PG stats");
nvgpu_falcon_print_dmem(pmu->flcn,
pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS],
sizeof(struct pmu_pg_stats_v2));
(u32)sizeof(struct pmu_pg_stats_v2));
g->ops.pmu.pmu_dump_elpg_stats(pmu);
}

2
drivers/gpu/nvgpu/common/pmu/pmu_gk20a.c
View File

@@ -821,7 +821,7 @@ void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
nvgpu_falcon_copy_from_dmem(pmu->flcn,
pmu->stat_dmem_offset[pg_engine_id],
(u8 *)&stats, sizeof(struct pmu_pg_stats), 0);
(u8 *)&stats, (u32)sizeof(struct pmu_pg_stats), 0);
pg_stat_data->ingating_time = stats.pg_ingating_time_us;
pg_stat_data->ungating_time = stats.pg_ungating_time_us;

2
drivers/gpu/nvgpu/common/pmu/pmu_gp106.c
View File

@@ -171,7 +171,7 @@ void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
nvgpu_falcon_copy_from_dmem(pmu->flcn,
pmu->stat_dmem_offset[pg_engine_id],
(u8 *)&stats, sizeof(struct pmu_pg_stats_v2), 0);
(u8 *)&stats, (u32)sizeof(struct pmu_pg_stats_v2), 0);
pg_stat_data->ingating_time = stats.total_sleep_time_us;
pg_stat_data->ungating_time = stats.total_non_sleep_time_us;

2
drivers/gpu/nvgpu/common/pmu/pmu_gp10b.c
View File

@@ -265,7 +265,7 @@ void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
nvgpu_falcon_copy_from_dmem(pmu->flcn,
pmu->stat_dmem_offset[pg_engine_id],
(u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0);
(u8 *)&stats, (u32)sizeof(struct pmu_pg_stats_v1), 0);
pg_stat_data->ingating_time = stats.total_sleep_timeus;
pg_stat_data->ungating_time = stats.total_nonsleep_timeus;

4
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
View File

@@ -98,8 +98,8 @@ struct pmu_hdr {
#define NV_FLCN_UNIT_ID_REWIND (0x00U)
#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr)
#define PMU_MSG_HDR_SIZE U32(sizeof(struct pmu_hdr))
#define PMU_CMD_HDR_SIZE U32(sizeof(struct pmu_hdr))
#define nv_pmu_hdr pmu_hdr
typedef u8 flcn_status;