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gpu: nvgpu: initialize masks for the perfmon counters 3

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Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.

Bug 2833620

Change-Id: I026ab236fd42f4f9c61e2f9b1f2b7988711a2927
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
(cherry picked from commit bbef4c6927)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422675
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
David Ung
2020-04-24 17:46:15 -07:00
committed by Alex Waterman
parent 47c30eb80f
commit 26de95b55f
3 changed files with 17 additions and 0 deletions
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4
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
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@@ -85,6 +85,10 @@ void gk20a_pmu_init_perfmon_counter(struct gk20a *g)
pwr_pmu_idle_mask_gr_enabled_f() |
pwr_pmu_idle_mask_ce_2_enabled_f());
/* assign same mask setting from GR ELPG to counter #3 */
data = gk20a_readl(g, pwr_pmu_idle_mask_1_supp_r(0));
gk20a_writel(g, pwr_pmu_idle_mask_1_r(3), data);
/* disable idle filtering for counters 3 and 6 */
data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3));
data = set_field(data, pwr_pmu_idle_ctrl_value_m() |