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gpu: nvgpu: Updated with generator headers

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Add pmu_idle_mask_1, pmu_idle_mask_2 and pmu_idle_mask_2_supp

Bug 2833620

Change-Id: I616ea584646c6affacc3df4c63ccff59d574ab52
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422614
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
David Ung
2020-10-01 12:53:58 -07:00
committed by Alex Waterman
parent d3f5905a0c
commit 47c30eb80f
4 changed files with 16 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pwr_gk20a.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2012-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -212,6 +212,8 @@
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U)
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_mask_1_r(i)\
(nvgpu_safe_add_u32(0x0010aa34U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -223,6 +223,8 @@
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U)
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_mask_1_r(i)\
(nvgpu_safe_add_u32(0x0010aa34U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pwr_gp10b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -224,6 +224,8 @@
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U)
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_mask_1_r(i)\
(nvgpu_safe_add_u32(0x0010aa34U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)

8
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -264,6 +264,10 @@
(nvgpu_safe_add_u32(0x0010a504U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_mask_gr_enabled_f() (0x1U)
#define pwr_pmu_idle_mask_ce_2_enabled_f() (0x200000U)
#define pwr_pmu_idle_mask_1_r(i)\
(nvgpu_safe_add_u32(0x0010aa34U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_mask_2_r(i)\
(nvgpu_safe_add_u32(0x0010a840U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_count_r(i)\
(nvgpu_safe_add_u32(0x0010a508U, nvgpu_safe_mult_u32((i), 16U)))
#define pwr_pmu_idle_count_value_f(v) ((U32(v) & 0x7fffffffU) << 0U)
@@ -293,6 +297,8 @@
(nvgpu_safe_add_u32(0x0010a9f0U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_mask_1_supp_r(i)\
(nvgpu_safe_add_u32(0x0010a9f4U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_idle_mask_2_supp_r(i)\
(nvgpu_safe_add_u32(0x0010a690U, nvgpu_safe_mult_u32((i), 4U)))
#define pwr_pmu_idle_ctrl_supp_r(i)\
(nvgpu_safe_add_u32(0x0010aa30U, nvgpu_safe_mult_u32((i), 8U)))
#define pwr_pmu_debug_r(i)\