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gpu: nvgpu: initialize masks for the perfmon counters 3

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Initialize the perfmon counters #3 masks to be same values as ELPG.
Hardware boots up with value NV_PPWR_PMU_IDLE_MASK_1(3) (0x10aa4c) = 0x1030,
but ELPG NV_PPWR_PMU_IDLE_MASK_1_SUPP(0) (0x10a9f4) boots up with 0.

Bug 2833620

Change-Id: I026ab236fd42f4f9c61e2f9b1f2b7988711a2927
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335299
(cherry picked from commit bbef4c6927)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422675
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
David Ung
2020-04-24 17:46:15 -07:00
committed by Alex Waterman
parent 47c30eb80f
commit 26de95b55f
3 changed files with 17 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -85,6 +85,10 @@ void gk20a_pmu_init_perfmon_counter(struct gk20a *g)
pwr_pmu_idle_mask_gr_enabled_f() |
pwr_pmu_idle_mask_ce_2_enabled_f());
/* assign same mask setting from GR ELPG to counter #3 */
data = gk20a_readl(g, pwr_pmu_idle_mask_1_supp_r(0));
gk20a_writel(g, pwr_pmu_idle_mask_1_r(3), data);
/* disable idle filtering for counters 3 and 6 */
data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3));
data = set_field(data, pwr_pmu_idle_ctrl_value_m() |

12
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.c
View File

@@ -33,6 +33,7 @@
#include <nvgpu/pmu/cmd.h>
#endif
#include "pmu_gk20a.h"
#include "pmu_gv11b.h"
#include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
@@ -113,6 +114,17 @@ static struct pg_init_sequence_list _pginitseq_gv11b[] = {
{0x00020004U, 0x00000000U} ,
};
void gv11b_pmu_init_perfmon_counter(struct gk20a *g)
{
u32 data;
gk20a_pmu_init_perfmon_counter(g);
/* assign same mask setting from GR ELPG to counter #3 */
data = gk20a_readl(g, pwr_pmu_idle_mask_2_supp_r(0));
gk20a_writel(g, pwr_pmu_idle_mask_2_r(3), data);
}
void gv11b_pmu_setup_elpg(struct gk20a *g)
{
size_t reg_writes;

1
drivers/gpu/nvgpu/hal/pmu/pmu_gv11b.h
View File

@@ -42,6 +42,7 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0);
#ifdef CONFIG_NVGPU_LS_PMU
int gv11b_pmu_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
u32 args_offset);
void gv11b_pmu_init_perfmon_counter(struct gk20a *g);
void gv11b_pmu_setup_elpg(struct gk20a *g);
void gv11b_secured_pmu_start(struct gk20a *g);
void gv11b_write_dmatrfbase(struct gk20a *g, u32 addr);