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gpu: nvgpu: Change clk load command to RPC

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- Added RPC infra for clock domain load from cmd.

NVGPU-3731

Change-Id: Id5240ad83d1a67ff77e9c61b5673e7eb4c22cff1
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153109
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-07-15 09:58:26 +05:30
committed by mobile promotions
parent 9c9bec40da
commit 28af1331c8
1 changed files with 10 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

83
drivers/gpu/nvgpu/common/pmu/clk/clk_domain.c
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@@ -39,30 +39,6 @@
#include "clk_domain.h"
#include "clk_prog.h"
struct nvgpu_clk_domain_rpc_pmucmdhandler_params {
struct nv_pmu_clk_rpc *prpccall;
u32 success;
};
static void nvgpu_clk_domain_rpc_pmucmdhandler(struct gk20a *g,
struct pmu_msg *msg, void *param, u32 status)
{
struct nvgpu_clk_domain_rpc_pmucmdhandler_params *phandlerparams =
(struct nvgpu_clk_domain_rpc_pmucmdhandler_params *)param;
nvgpu_log_info(g, " ");
if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) {
nvgpu_err(g, "unsupported msg for CLK LOAD RPC %x",
msg->msg.clk.msg_type);
return;
}
if (phandlerparams->prpccall->b_supported) {
phandlerparams->success = 1;
}
}
static struct nvgpu_clk_domain *construct_clk_domain(struct gk20a *g,
void *pargs);
@@ -1404,62 +1380,23 @@ done:
int nvgpu_clk_pmu_clk_domains_load(struct gk20a *g)
{
struct pmu_cmd cmd;
struct pmu_payload payload;
struct nv_pmu_clk_rpc rpccall;
struct nvgpu_clk_domain_rpc_pmucmdhandler_params handler;
struct nv_pmu_clk_load *clkload;
int status;
struct nvgpu_pmu *pmu = g->pmu;
struct nv_pmu_rpc_struct_clk_load clk_load_rpc;
(void) memset(&payload, 0, sizeof(struct pmu_payload));
(void) memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
(void) memset(&handler, 0, sizeof(
struct nvgpu_clk_domain_rpc_pmucmdhandler_params));
(void) memset(&clk_load_rpc, 0,
sizeof(struct nv_pmu_rpc_struct_clk_load));
rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
clkload = &rpccall.params.clk_load;
clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_CLK_DOMAIN;
cmd.hdr.unit_id = PMU_UNIT_CLK;
cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
(u32)sizeof(struct pmu_hdr);
cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
cmd.cmd.clk.generic.b_perf_daemon_cmd = false;
payload.in.buf = (u8 *)&rpccall;
payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
nvgpu_assert(NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET < U64(U32_MAX));
payload.in.offset = (u32)NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
payload.out.buf = (u8 *)&rpccall;
payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
nvgpu_assert(NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET < U64(U32_MAX));
payload.out.offset = (u32)NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
handler.prpccall = &rpccall;
handler.success = 0;
status = nvgpu_pmu_cmd_post(g, &cmd, &payload,
PMU_COMMAND_QUEUE_LPQ,
nvgpu_clk_domain_rpc_pmucmdhandler, (void *)&handler);
clk_load_rpc.clk_load.feature = NV_NV_PMU_CLK_LOAD_FEATURE_CLK_DOMAIN;
/* Continue with PMU setup, assume FB map is done */
PMU_RPC_EXECUTE_CPB(status, pmu, CLK, LOAD, &clk_load_rpc, 0);
if (status != 0) {
nvgpu_err(g, "unable to post clk RPC cmd %x",
cmd.cmd.clk.cmd_type);
goto done;
nvgpu_err(g,
"Failed to execute Clock domain Load RPC status=0x%x",
status);
}
(void) pmu_wait_message_cond(g->pmu, nvgpu_get_poll_timeout(g),
&handler.success, 1);
if (handler.success == 0U) {
nvgpu_err(g, "rpc call to load clk_domains cal failed");
status = -EINVAL;
}
done:
return status;
}