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gpu: nvgpu: enable CONFIG_NVGPU_LS_PMU for safety

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Enable CONFIG_NVGPU_LS_PMU for dGPU safety build.
Add missing #ifdefs for CONFIG_NVGPU_POWER_PG and
CONFIG_NVGPU_CLK_ARB which are not defined for safety build.

Moved gm20b_mc_is_enabled to fusa code.

NVGPU_UNIT_PWR is only defined when CONFIG_NVGPU_HAL_NON_FUSA
is defined. Added #ifdefs to compile out gk20a_pmu functions
that are using it.

Jira NVGPU-4661

Change-Id: Ieb552f9374bad6f3dad777322f118931e0bc94ec
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317085
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Thomas Fleury
2020-03-20 11:06:40 -04:00
committed by Alex Waterman
parent 1adf23eea5
commit 28ccd63f69
9 changed files with 49 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/Makefile.shared.configs
View File

@@ -117,6 +117,9 @@ NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_SM_DIVERSITY
CONFIG_NVGPU_USE_3LSS_ERR_INJECTION := 1 CONFIG_NVGPU_USE_3LSS_ERR_INJECTION := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_USE_3LSS_ERR_INJECTION NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_USE_3LSS_ERR_INJECTION
CONFIG_NVGPU_LS_PMU := 1
NVGPU_COMMON_CFLAGS += -DCONFIG_NVGPU_LS_PMU
endif endif
endif endif

18
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -326,7 +326,8 @@ srcs += hal/gr/falcon/gr_falcon_gm20b.c \
hal/fb/fb_gp106.c \ hal/fb/fb_gp106.c \
hal/falcon/falcon_gk20a.c \ hal/falcon/falcon_gk20a.c \
hal/bus/bus_gk20a.c \ hal/bus/bus_gk20a.c \
hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c \
hal/pmu/pmu_gv11b.c
endif endif
endif endif
@@ -475,12 +476,6 @@ srcs += \
common/pmu/perfmon/pmu_perfmon.c \ common/pmu/perfmon/pmu_perfmon.c \
common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \ common/pmu/perfmon/pmu_perfmon_sw_gm20b.c \
common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \ common/pmu/perfmon/pmu_perfmon_sw_gv11b.c \
common/pmu/pg/pg_sw_gm20b.c \
common/pmu/pg/pg_sw_gp10b.c \
common/pmu/pg/pg_sw_gp106.c \
common/pmu/pg/pg_sw_gv11b.c \
common/pmu/pg/pmu_pg.c \
common/pmu/pg/pmu_aelpg.c \
common/pmu/pmgr/pmgr.c \ common/pmu/pmgr/pmgr.c \
common/pmu/pmgr/pmgrpmu.c \ common/pmu/pmgr/pmgrpmu.c \
common/pmu/pmgr/pwrdev.c \ common/pmu/pmgr/pwrdev.c \
@@ -504,6 +499,15 @@ srcs += \
hal/pmu/pmu_gp10b.c \ hal/pmu/pmu_gp10b.c \
hal/pmu/pmu_tu104.c hal/pmu/pmu_tu104.c
ifeq ($(CONFIG_NVGPU_POWER_PG),1)
srcs += common/pmu/pg/pg_sw_gm20b.c \
common/pmu/pg/pg_sw_gp10b.c \
common/pmu/pg/pg_sw_gp106.c \
common/pmu/pg/pg_sw_gv11b.c \
common/pmu/pg/pmu_pg.c \
common/pmu/pg/pmu_aelpg.c
endif
ifeq ($(CONFIG_NVGPU_CLK_ARB),1) ifeq ($(CONFIG_NVGPU_CLK_ARB),1)
srcs += common/clk_arb/clk_arb_gv100.c srcs += common/clk_arb/clk_arb_gv100.c
endif endif

4
drivers/gpu/nvgpu/common/gr/obj_ctx.c
View File

@@ -716,7 +716,7 @@ int nvgpu_gr_obj_ctx_alloc_golden_ctx_image(struct gk20a *g,
} }
golden_image->ready = true; golden_image->ready = true;
#ifdef CONFIG_NVGPU_LS_PMU #ifdef CONFIG_NVGPU_POWER_PG
nvgpu_pmu_set_golden_image_initialized(g, true); nvgpu_pmu_set_golden_image_initialized(g, true);
#endif #endif
g->ops.gr.falcon.set_current_ctx_invalid(g); g->ops.gr.falcon.set_current_ctx_invalid(g);
@@ -923,7 +923,7 @@ void nvgpu_gr_obj_ctx_deinit(struct gk20a *g,
golden_image->local_golden_image); golden_image->local_golden_image);
golden_image->local_golden_image = NULL; golden_image->local_golden_image = NULL;
} }
#ifdef CONFIG_NVGPU_LS_PMU #ifdef CONFIG_NVGPU_POWER_PG
nvgpu_pmu_set_golden_image_initialized(g, false); nvgpu_pmu_set_golden_image_initialized(g, false);
#endif #endif
golden_image->ready = false; golden_image->ready = false;

2
drivers/gpu/nvgpu/common/pmu/clk/clk_vf_point.c
View File

@@ -494,7 +494,9 @@ int clk_vf_point_init_pmupstate(struct gk20a *g)
return -ENOMEM; return -ENOMEM;
} }
#ifdef CONFIG_NVGPU_CLK_ARB
g->pmu->clk_pmu->nvgpu_clk_vf_point_cache = nvgpu_clk_vf_point_cache; g->pmu->clk_pmu->nvgpu_clk_vf_point_cache = nvgpu_clk_vf_point_cache;
#endif
return 0; return 0;
} }

2
drivers/gpu/nvgpu/common/pmu/perf/perf.c
View File

@@ -51,7 +51,9 @@ static int pmu_set_boot_clk_runcb_fn(void *arg)
} }
vfe_init->state_change = false; vfe_init->state_change = false;
#ifdef CONFIG_NVGPU_CLK_ARB
nvgpu_clk_arb_schedule_vf_table_update(g); nvgpu_clk_arb_schedule_vf_table_update(g);
#endif
} }
return 0; return 0;

20
drivers/gpu/nvgpu/common/pmu/pmu_rtos_init.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -31,17 +31,19 @@
#include <nvgpu/boardobjgrp.h> #include <nvgpu/boardobjgrp.h>
#include <nvgpu/pmu.h> #include <nvgpu/pmu.h>
#include <nvgpu/pmu/pmu_pg.h>
#include <nvgpu/pmu/mutex.h> #include <nvgpu/pmu/mutex.h>
#include <nvgpu/pmu/seq.h> #include <nvgpu/pmu/seq.h>
#include <nvgpu/pmu/lsfm.h> #include <nvgpu/pmu/lsfm.h>
#include <nvgpu/pmu/super_surface.h> #include <nvgpu/pmu/super_surface.h>
#include <nvgpu/pmu/pmu_perfmon.h> #include <nvgpu/pmu/pmu_perfmon.h>
#include <nvgpu/pmu/pmu_pg.h>
#include <nvgpu/pmu/fw.h> #include <nvgpu/pmu/fw.h>
#include <nvgpu/pmu/debug.h> #include <nvgpu/pmu/debug.h>
#include <nvgpu/pmu/pmu_pstate.h> #include <nvgpu/pmu/pmu_pstate.h>
#ifdef CONFIG_NVGPU_POWER_PG
#include <nvgpu/pmu/pmu_pg.h>
#endif
#ifdef CONFIG_NVGPU_DGPU #ifdef CONFIG_NVGPU_DGPU
#include <nvgpu/sec2/lsfm.h> #include <nvgpu/sec2/lsfm.h>
#endif #endif
@@ -58,9 +60,11 @@ int nvgpu_pmu_lock_acquire(struct gk20a *g, struct nvgpu_pmu *pmu,
return 0; return 0;
} }
#ifdef CONFIG_NVGPU_POWER_PG
if (!pmu->pg->initialized) { if (!pmu->pg->initialized) {
return -EINVAL; return -EINVAL;
} }
#endif
return nvgpu_pmu_mutex_acquire(g, pmu->mutexes, id, token); return nvgpu_pmu_mutex_acquire(g, pmu->mutexes, id, token);
} }
@@ -76,9 +80,11 @@ int nvgpu_pmu_lock_release(struct gk20a *g, struct nvgpu_pmu *pmu,
return 0; return 0;
} }
#ifdef CONFIG_PMU_POWER_PG
if (!pmu->pg->initialized) { if (!pmu->pg->initialized) {
return -EINVAL; return -EINVAL;
} }
#endif
return nvgpu_pmu_mutex_release(g, pmu->mutexes, id, token); return nvgpu_pmu_mutex_release(g, pmu->mutexes, id, token);
} }
@@ -88,9 +94,11 @@ int nvgpu_pmu_destroy(struct gk20a *g, struct nvgpu_pmu *pmu)
{ {
nvgpu_log_fn(g, " "); nvgpu_log_fn(g, " ");
#ifdef CONFIG_NVGPU_POWER_PG
if (g->can_elpg) { if (g->can_elpg) {
nvgpu_pmu_pg_destroy(g, pmu, pmu->pg); nvgpu_pmu_pg_destroy(g, pmu, pmu->pg);
} }
#endif
nvgpu_pmu_queues_free(g, &pmu->queues); nvgpu_pmu_queues_free(g, &pmu->queues);
@@ -144,7 +152,9 @@ static void remove_pmu_support(struct nvgpu_pmu *pmu)
nvgpu_pmu_debug_deinit(g, pmu); nvgpu_pmu_debug_deinit(g, pmu);
nvgpu_pmu_lsfm_deinit(g, pmu, pmu->lsfm); nvgpu_pmu_lsfm_deinit(g, pmu, pmu->lsfm);
#ifdef CONFIG_PMU_POWER_PG
nvgpu_pmu_pg_deinit(g, pmu, pmu->pg); nvgpu_pmu_pg_deinit(g, pmu, pmu->pg);
#endif
nvgpu_pmu_sequences_deinit(g, pmu, pmu->sequences); nvgpu_pmu_sequences_deinit(g, pmu, pmu->sequences);
nvgpu_pmu_mutexe_deinit(g, pmu, pmu->mutexes); nvgpu_pmu_mutexe_deinit(g, pmu, pmu->mutexes);
nvgpu_pmu_fw_deinit(g, pmu, pmu->fw); nvgpu_pmu_fw_deinit(g, pmu, pmu->fw);
@@ -163,12 +173,14 @@ static int pmu_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu )
/* set default value to sequences */ /* set default value to sequences */
nvgpu_pmu_sequences_sw_setup(g, pmu, pmu->sequences); nvgpu_pmu_sequences_sw_setup(g, pmu, pmu->sequences);
#ifdef CONFIG_NVGPU_POWER_PG
if (g->can_elpg) { if (g->can_elpg) {
err = nvgpu_pmu_pg_sw_setup(g, pmu, pmu->pg); err = nvgpu_pmu_pg_sw_setup(g, pmu, pmu->pg);
if (err != 0){ if (err != 0){
goto exit; goto exit;
} }
} }
#endif
if (pmu->sw_ready) { if (pmu->sw_ready) {
nvgpu_log_fn(g, "skip PMU-RTOS shared buffer realloc"); nvgpu_log_fn(g, "skip PMU-RTOS shared buffer realloc");
@@ -295,12 +307,14 @@ int nvgpu_pmu_rtos_early_init(struct gk20a *g, struct nvgpu_pmu *pmu)
goto init_failed; goto init_failed;
} }
#ifdef CONFIG_NVGPU_POWER_PG
if (g->can_elpg) { if (g->can_elpg) {
err = nvgpu_pmu_pg_init(g, pmu, &pmu->pg); err = nvgpu_pmu_pg_init(g, pmu, &pmu->pg);
if (err != 0) { if (err != 0) {
goto init_failed; goto init_failed;
} }
} }
#endif
err = nvgpu_pmu_lsfm_init(g, &pmu->lsfm); err = nvgpu_pmu_lsfm_init(g, &pmu->lsfm);
if (err != 0) { if (err != 0) {

8
drivers/gpu/nvgpu/hal/mc/mc_gm20b.c
View File

@@ -300,11 +300,3 @@ bool gm20b_mc_is_mmu_fault_pending(struct gk20a *g)
return g->ops.fifo.is_mmu_fault_pending(g); return g->ops.fifo.is_mmu_fault_pending(g);
} }
#ifdef CONFIG_NVGPU_LS_PMU
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = g->ops.mc.reset_mask(g, unit);
return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
}
#endif

9
drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
View File

@@ -164,3 +164,12 @@ u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit)
return mask; return mask;
} }
#ifdef CONFIG_NVGPU_LS_PMU
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit)
{
u32 mask = g->ops.mc.reset_mask(g, unit);
return (nvgpu_readl(g, mc_enable_r()) & mask) != 0U;
}
#endif

4
drivers/gpu/nvgpu/hal/pmu/pmu_gk20a.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -688,6 +688,7 @@ int gk20a_pmu_ns_bootstrap(struct gk20a *g, struct nvgpu_pmu *pmu,
return err; return err;
} }
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) bool gk20a_pmu_is_engine_in_reset(struct gk20a *g)
{ {
bool status = false; bool status = false;
@@ -707,6 +708,7 @@ void gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset)
g->ops.mc.disable(g, reset_mask); g->ops.mc.disable(g, reset_mask);
} }
} }
#endif
void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
{ {