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gpu: nvgpu: remove round_up usage in safety build
- In function gv11b_tsg_init_eng_method_buffers() PAGE_ALIGN can be used instead of round_up macro. - In function nvgpu_posix_find_next_bit() rounding up of start does not seem to serve any purpose. JIRA NVGPU-7057 Change-Id: I4a3a21e95a0f3aa38f7007de1f6959f1d878e511 Signed-off-by: shashank singh <shashsingh@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2614326 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2672107 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> GVS: Gerrit_Virtual_Submit
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -111,7 +111,6 @@ int gv11b_tsg_init_eng_method_buffers(struct gk20a *g, struct nvgpu_tsg *tsg)
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int err = 0;
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int i;
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unsigned int runque, buffer_size;
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u32 page_size = U32(NVGPU_CPU_PAGE_SIZE);
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unsigned int num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
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if (tsg->eng_method_buffers != NULL) {
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@@ -122,7 +121,7 @@ int gv11b_tsg_init_eng_method_buffers(struct gk20a *g, struct nvgpu_tsg *tsg)
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buffer_size = nvgpu_safe_add_u32(nvgpu_safe_mult_u32((9U + 1U + 3U),
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g->ops.ce.get_num_pce(g)), 2U);
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buffer_size = nvgpu_safe_mult_u32((27U * 5U), buffer_size);
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buffer_size = round_up(buffer_size, page_size);
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buffer_size = PAGE_ALIGN(buffer_size);
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nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size);
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tsg->eng_method_buffers = nvgpu_kzalloc(g,
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@@ -216,6 +216,7 @@
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*/
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#define round_mask(x, y) ((__typeof__(x))((y) - 1U))
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#ifdef CONFIG_NVGPU_NON_FUSA
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/**
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* @brief Round up the value of its argument \a x.
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*
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@@ -229,6 +230,7 @@
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* @return Rounded up value of \a x.
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*/
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#define round_up(x, y) ((((x) - 1U) | round_mask(x, y)) + 1U)
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#endif
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/**
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* @brief Round down the value of its argument \a x.
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -111,8 +111,6 @@ static unsigned long nvgpu_posix_find_next_bit(const unsigned long *address,
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idx = start / BITS_PER_LONG;
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w = (base_addr[idx] ^ invert_mask) & start_mask;
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start = round_up(start, BITS_PER_LONG);
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idx_max = (n - 1UL) / BITS_PER_LONG;
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/*
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@@ -125,8 +123,6 @@ static unsigned long nvgpu_posix_find_next_bit(const unsigned long *address,
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return n;
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}
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start = nvgpu_safe_add_u64(start, BITS_PER_LONG);
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w = base_addr[idx] ^ invert_mask;
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}
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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@@ -460,7 +460,7 @@ int test_round_macros(struct unit_module *m,
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"round_mask failure %d\n", result);
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}
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}
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#ifdef CONFIG_NVGPU_NON_FUSA
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result = ROUND_BY_VALUE;
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for (i = 0; i < ROUND_BY_VALUE; i++) {
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test1 = (ROUND_DOWN_RESULT + 1U) + i;
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@@ -468,6 +468,7 @@ int test_round_macros(struct unit_module *m,
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unit_return_fail(m, "round_up failure %d %d\n", test1, i);
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}
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}
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#endif
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result = ROUND_BY_VALUE;
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for (i = 0; i < ROUND_BY_VALUE; i++) {
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