gpu: nvgpu: enable HWPM Mode-E context switch

- This patch enables HWPM Mode-E context switch for gv11b.
- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.
- For Mode-E ctxsw it is required that engine_sel
is set to 0xFFFFFFFF.
- Default 0 is a valid signal and causes problems.

Bug 2106999

Change-Id: Idc6380116a71ffd7ae348ceec68cb395b2eca5f6
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818070
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -328,7 +328,12 @@ static const struct gpu_ops gv11b_ops = {
 		.enable_exceptions = gr_gv11b_enable_exceptions,
 		.get_lrf_tex_ltc_dram_override = get_ecc_override_val,
 		.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
+		.get_hw_accessor_stream_out_mode =
+			gr_gv100_get_hw_accessor_stream_out_mode,
+		.get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon,
+		.set_pmm_register = gr_gv100_set_pmm_register,
 		.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
+		.init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register,
 		.record_sm_error_state = gv11b_gr_record_sm_error_state,
 		.clear_sm_error_state = gm20b_gr_clear_sm_error_state,
 		.suspend_contexts = gr_gp10b_suspend_contexts,

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -144,6 +144,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
 	return 0x0U;
 }
+static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void)
+{
+	return 0x2U;
+}
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
 	return 0x7U << 3U;

drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h

@@ -60,6 +60,10 @@ static inline u32 perf_pmmgpc_perdomain_offset_v(void)
 {
 	return 0x00000200U;
 }
+static inline u32 perf_pmmsys_perdomain_offset_v(void)
+{
+	return 0x00000200U;
+}
 static inline u32 perf_pmmgpc_base_v(void)
 {
 	return 0x00180000U;
@@ -232,4 +236,28 @@ static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
 {
 	return 0x10U;
 }
+static inline u32 perf_pmmsys_engine_sel_r(u32 i)
+{
+	return 0x0024006cU + i*512U;
+}
+static inline u32 perf_pmmsys_engine_sel__size_1_v(void)
+{
+	return 0x00000020U;
+}
+static inline u32 perf_pmmfbp_engine_sel_r(u32 i)
+{
+	return 0x0020006cU + i*512U;
+}
+static inline u32 perf_pmmfbp_engine_sel__size_1_v(void)
+{
+	return 0x00000020U;
+}
+static inline u32 perf_pmmgpc_engine_sel_r(u32 i)
+{
+	return 0x0018006cU + i*512U;
+}
+static inline u32 perf_pmmgpc_engine_sel__size_1_v(void)
+{
+	return 0x00000020U;
+}
 #endif

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -81,6 +81,8 @@
 #include <gv11b/gr_ctx_gv11b.h>
 #include <gv11b/gr_gv11b.h>
 
+#include <gv100/gr_gv100.h>
+
 #include <nvgpu/enabled.h>
 #include <nvgpu/channel.h>
 
@@ -183,6 +185,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.enable_exceptions = NULL,
 		.get_lrf_tex_ltc_dram_override = NULL,
 		.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
+		.get_hw_accessor_stream_out_mode =
+			gr_gv100_get_hw_accessor_stream_out_mode,
 		.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
 		.record_sm_error_state = gv11b_gr_record_sm_error_state,
 		.clear_sm_error_state = vgpu_gr_clear_sm_error_state,