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gpu: nvgpu: debug dump tsg domain name

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Include the scheduling domain name in the channel debug dump. The domain
name of a channel is the domain name of its parent TSG, if any. Copy
just the name into the dump info to avoid refcounting concerns.

While at it, reword the deterministic flag for less ambiguity.

Jira NVGPU-6791

Change-Id: I06041277f938e20f23de9aa419cfffbaa028035e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2673101
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Konsta Hölttä
2022-02-23 12:11:39 +02:00
committed by mobile promotions
parent f10ee4ab0e
commit 2ab6184955
2 changed files with 19 additions and 2 deletions
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20
drivers/gpu/nvgpu/common/fifo/channel.c
View File

@@ -66,6 +66,7 @@
#include <nvgpu/job.h> #include <nvgpu/job.h>
#include <nvgpu/priv_cmdbuf.h> #include <nvgpu/priv_cmdbuf.h>
#include <nvgpu/string.h> #include <nvgpu/string.h>
#include <nvgpu/nvs.h>
#include "channel_wdt.h" #include "channel_wdt.h"
#include "channel_worker.h" #include "channel_worker.h"
@@ -2135,13 +2136,14 @@ static void nvgpu_channel_info_debug_dump(struct gk20a *g,
*/ */
u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl); u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl);
gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d%s: ", gk20a_debug_output(o, "%d-%s, TSG: %u, pid %d, refs: %d, deterministic: %s, domain name: %s",
info->chid, info->chid,
g->name, g->name,
info->tsgid, info->tsgid,
info->pid, info->pid,
info->refs, info->refs,
info->deterministic ? ", deterministic" : ""); info->deterministic ? "yes" : "no",
info->nvs_domain_name);
gk20a_debug_output(o, "channel status: %s in use %s %s", gk20a_debug_output(o, "channel status: %s in use %s %s",
info->hw_state.enabled ? "" : "not", info->hw_state.enabled ? "" : "not",
info->hw_state.status_string, info->hw_state.status_string,
@@ -2214,6 +2216,8 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
for (chid = 0U; chid < f->num_channels; chid++) { for (chid = 0U; chid < f->num_channels; chid++) {
struct nvgpu_channel *ch = &f->channel[chid]; struct nvgpu_channel *ch = &f->channel[chid];
struct nvgpu_channel_dump_info *info = infos[chid]; struct nvgpu_channel_dump_info *info = infos[chid];
struct nvgpu_tsg *tsg;
const char *domain_name;
#ifdef CONFIG_NVGPU_SW_SEMAPHORE #ifdef CONFIG_NVGPU_SW_SEMAPHORE
struct nvgpu_channel_sync_semaphore *sync_sema; struct nvgpu_channel_sync_semaphore *sync_sema;
struct nvgpu_hw_semaphore *hw_sema = NULL; struct nvgpu_hw_semaphore *hw_sema = NULL;
@@ -2232,11 +2236,23 @@ void nvgpu_channel_debug_dump_all(struct gk20a *g,
continue; continue;
} }
tsg = nvgpu_tsg_from_ch(ch);
info->chid = ch->chid; info->chid = ch->chid;
info->tsgid = ch->tsgid; info->tsgid = ch->tsgid;
info->pid = ch->pid; info->pid = ch->pid;
info->refs = nvgpu_atomic_read(&ch->ref_count); info->refs = nvgpu_atomic_read(&ch->ref_count);
info->deterministic = nvgpu_channel_is_deterministic(ch); info->deterministic = nvgpu_channel_is_deterministic(ch);
if (tsg) {
if (tsg->nvs_domain) {
domain_name = nvgpu_nvs_domain_get_name(tsg->nvs_domain);
} else {
domain_name = "(no domain)";
}
} else {
domain_name = "(no tsg)";
}
(void)strncpy(info->nvs_domain_name, domain_name,
sizeof(info->nvs_domain_name) - 1U);
#ifdef CONFIG_NVGPU_SW_SEMAPHORE #ifdef CONFIG_NVGPU_SW_SEMAPHORE
if (hw_sema != NULL) { if (hw_sema != NULL) {

1
drivers/gpu/nvgpu/include/nvgpu/channel.h
View File

@@ -218,6 +218,7 @@ struct nvgpu_channel_dump_info {
u32 next; u32 next;
u64 addr; u64 addr;
} sema; } sema;
char nvs_domain_name[32];
}; };
/** /**