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gpu: nvgpu: Disable only channel at zcull bind

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At zcull bind we disable whole GR engine. This is unnecessary, so
instead disable only the channel and make sure it's unloaded.

Introduces also an API in fifo_gk20a.c to do the channel disable.

gr_gk20a_ctx_zcull_setup() was always passed true as last parameter,
so remove parameter.

Change-Id: I7ae6e101ec7d1ab3f6ee4e9bcc442d23dbd21247
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/787570
This commit is contained in:
Terje Bergstrom
2015-08-05 11:00:39 -07:00
parent 75c09b96b4
commit 2aead8a72f
4 changed files with 13 additions and 22 deletions
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1
drivers/gpu/nvgpu/gk20a/channel_gk20a.c
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@@ -2538,6 +2538,7 @@ void gk20a_init_channel(struct gpu_ops *gops)
gops->fifo.bind_channel = channel_gk20a_bind;
gops->fifo.unbind_channel = channel_gk20a_unbind;
gops->fifo.disable_channel = channel_gk20a_disable;
gops->fifo.enable_channel = channel_gk20a_enable;
gops->fifo.alloc_inst = channel_gk20a_alloc_inst;
gops->fifo.free_inst = channel_gk20a_free_inst;
gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc;

1
drivers/gpu/nvgpu/gk20a/gk20a.h
View File

@@ -222,6 +222,7 @@ struct gpu_ops {
void (*bind_channel)(struct channel_gk20a *ch_gk20a);
void (*unbind_channel)(struct channel_gk20a *ch_gk20a);
void (*disable_channel)(struct channel_gk20a *ch);
void (*enable_channel)(struct channel_gk20a *ch);
int (*alloc_inst)(struct gk20a *g, struct channel_gk20a *ch);
void (*free_inst)(struct gk20a *g, struct channel_gk20a *ch);
int (*setup_ramfc)(struct channel_gk20a *c, u64 gpfifo_base,

32
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -703,12 +703,9 @@ static int gr_gk20a_fecs_ctx_bind_channel(struct gk20a *g,
return ret;
}
static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
bool disable_fifo)
static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c)
{
struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
struct fifo_gk20a *f = &g->fifo;
struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A;
u32 va_lo, va_hi, va;
int ret = 0;
void *ctx_ptr = NULL;
@@ -732,30 +729,21 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c,
va_hi = u64_hi32(ch_ctx->zcull_ctx.gpu_va);
va = ((va_lo >> 8) & 0x00FFFFFF) | ((va_hi << 24) & 0xFF000000);
if (disable_fifo) {
ret = gk20a_fifo_disable_engine_activity(g, gr_info, true);
if (ret) {
gk20a_err(dev_from_gk20a(g),
"failed to disable gr engine activity\n");
goto clean_up;
}
c->g->ops.fifo.disable_channel(c);
ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
if (ret) {
c->g->ops.fifo.enable_channel(c);
gk20a_err(dev_from_gk20a(g),
"failed to disable gr engine activity\n");
goto clean_up;
}
g->ops.mm.fb_flush(g);
gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_o(), 0,
ch_ctx->zcull_ctx.ctx_sw_mode);
gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_zcull_ptr_o(), 0, va);
if (disable_fifo) {
ret = gk20a_fifo_enable_engine_activity(g, gr_info);
if (ret) {
gk20a_err(dev_from_gk20a(g),
"failed to enable gr engine activity\n");
goto clean_up;
}
}
c->g->ops.fifo.enable_channel(c);
clean_up:
vunmap(ctx_ptr);
@@ -3343,7 +3331,7 @@ int gr_gk20a_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
zcull_ctx->gpu_va = zcull_va;
/* TBD: don't disable channel in sw method processing */
return gr_gk20a_ctx_zcull_setup(g, c, true);
return gr_gk20a_ctx_zcull_setup(g, c);
}
int gr_gk20a_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,

1
drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
View File

@@ -109,6 +109,7 @@ void gm20b_init_fifo(struct gpu_ops *gops)
gops->fifo.bind_channel = channel_gm20b_bind;
gops->fifo.unbind_channel = channel_gk20a_unbind;
gops->fifo.disable_channel = channel_gk20a_disable;
gops->fifo.enable_channel = channel_gk20a_enable;
gops->fifo.alloc_inst = channel_gk20a_alloc_inst;
gops->fifo.free_inst = channel_gk20a_free_inst;
gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc;