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gpu: nvgpu: update hw headers

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Update gm20b, gv11b, tu104 hw headers to resolve kernel checkpatch
warnings as below:
 Rule kernel_checkpatch: Fail
  	ERROR: need consistent spacing around '+' (ctx:WxV)
 #89: FILE: drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h:74:
 +		((U32(0x0U) << (16U +((i)*1U))))

Bug 3139301

Change-Id: Ib5a9bff0a6711355f6d2923be8184b7f243af24f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2524534
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Vedashree Vidwans
2021-05-04 10:44:07 -07:00
committed by mobile promotions
parent 636a70790b
commit 2b0b2e9b70
5 changed files with 19 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -102,8 +102,8 @@
#define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\ #define ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(v)\
((U32(v) & 0x1fU) << 16U) ((U32(v) & 0x1fU) << 16U)
#define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U) #define ltc_ltcs_ltss_dstg_zbc_index_r() (0x0017e338U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_s() (4U) #define ltc_ltcs_ltss_dstg_zbc_index_address_s() (4U)
#define ltc_ltcs_ltss_dstg_zbc_index_address_f(v) ((U32(v) & 0xfU) << 0U)
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\ #define ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i)\
(nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x0017e33cU, nvgpu_safe_mult_u32((i), 4U)))
#define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U) #define ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v() (0x00000004U)

2
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),

8
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_ce_tu104.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -78,14 +78,14 @@
#define ce_grce_config_r(i)\ #define ce_grce_config_r(i)\
(nvgpu_safe_add_u32(0x00104034U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00104034U, nvgpu_safe_mult_u32((i), 4U)))
#define ce_grce_config__size_1_v() (0x00000002U) #define ce_grce_config__size_1_v() (0x00000002U)
#define ce_grce_config_shared_lce_f(v) (((v)&0xfU) << 0U) #define ce_grce_config_shared_lce_f(v) ((U32(v) & 0xfU) << 0U)
#define ce_grce_config_shared_lce_none_f() (0xfU) #define ce_grce_config_shared_lce_none_f() (0xfU)
#define ce_grce_config_shared_f(v) (((v)&0x1U) << 30U) #define ce_grce_config_shared_f(v) ((U32(v) & 0x1U) << 30U)
#define ce_grce_config_timeslice_short_f() (0x0U) #define ce_grce_config_timeslice_short_f() (0x0U)
#define ce_grce_config_timeslice_long_f() (0x80000000U) #define ce_grce_config_timeslice_long_f() (0x80000000U)
#define ce_pce2lce_config_r(i)\ #define ce_pce2lce_config_r(i)\
(nvgpu_safe_add_u32(0x00104040U, nvgpu_safe_mult_u32((i), 4U))) (nvgpu_safe_add_u32(0x00104040U, nvgpu_safe_mult_u32((i), 4U)))
#define ce_pce2lce_config__size_1_v() (0x00000004U) #define ce_pce2lce_config__size_1_v() (0x00000004U)
#define ce_pce2lce_config_pce_assigned_lce_f(v) (((v)&0xfU) << 0U) #define ce_pce2lce_config_pce_assigned_lce_f(v) ((U32(v) & 0xfU) << 0U)
#define ce_pce2lce_config_pce_assigned_lce_none_f() (0xfU) #define ce_pce2lce_config_pce_assigned_lce_none_f() (0xfU)
#endif #endif

18
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fb_tu104.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -68,16 +68,16 @@
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_m(i)\
(U32(0x1U) << (16U + (i)*1U)) (U32(0x1U) << (16U + (i)*1U))
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_v(r, i)\
(((r) >> (16U + i*1U)) & 0x1U) (((r) >> (16U + (i)*1U)) & 0x1U)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\
((0x0U << (32U +((i)*1U)))) ((U32(0x0U) << (16U + ((i)*1U))))
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\
((0x1U << (32U +((i)*1U)))) ((U32(0x1U) << (16U + ((i)*1U))))
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U)
#define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ #define fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\
((0x0U << (32U +((i)*1U)))) ((U32(0x0U) << (16U + ((i)*1U))))
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v)\ #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(v)\
((U32(v) & 0x1U) << 25U) ((U32(v) & 0x1U) << 25U)
#define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) #define fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U)
@@ -137,16 +137,16 @@
#define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_m(i)\
(U32(0x1U) << (16U + (i)*1U)) (U32(0x1U) << (16U + (i)*1U))
#define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_v(r, i)\
(((r) >> (16U + i*1U)) & 0x1U) (((r) >> (16U + (i)*1U)) & 0x1U)
#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U) #define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v() (0x00000008U)
#define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(i)\
((0x0U << (32U +((i)*1U)))) ((U32(0x0U) << (16U + ((i)*1U))))
#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U) #define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v() (0x00000001U)
#define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(i)\
((0x1U << (32U +((i)*1U)))) ((U32(0x1U) << (16U + ((i)*1U))))
#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U) #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v() (0x00000000U)
#define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\ #define fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(i)\
((0x0U << (32U +((i)*1U)))) ((U32(0x0U) << (16U + ((i)*1U))))
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v)\ #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(v)\
((U32(v) & 0x1U) << 25U) ((U32(v) & 0x1U) << 25U)
#define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U) #define fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m() (U32(0x1U) << 25U)

4
drivers/gpu/nvgpu/include/nvgpu/hw/tu104/hw_fifo_tu104.h
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -112,7 +112,7 @@
#define fifo_intr_pbdma_id_status_f(v, i)\ #define fifo_intr_pbdma_id_status_f(v, i)\
((U32(v) & 0x1U) << (0U + (i)*1U)) ((U32(v) & 0x1U) << (0U + (i)*1U))
#define fifo_intr_pbdma_id_status_v(r, i)\ #define fifo_intr_pbdma_id_status_v(r, i)\
(((r) >> (0U + i*1U)) & 0x1U) (((r) >> (0U + (i)*1U)) & 0x1U)
#define fifo_intr_pbdma_id_status__size_1_v() (0x0000000cU) #define fifo_intr_pbdma_id_status__size_1_v() (0x0000000cU)
#define fifo_intr_runlist_r() (0x00002a00U) #define fifo_intr_runlist_r() (0x00002a00U)
#define fifo_fb_timeout_r() (0x00002a04U) #define fifo_fb_timeout_r() (0x00002a04U)