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gpu: nvgpu: add accessors for global_esr values and sm_dbgr_control

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Add gk20a/gm20b accessors for various global_esr values
and for sm_dbgr_control modes

Bug 200156699

Change-Id: If7fd8cd7567f8bcd1f645facf9553bdc0a153526
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1120333
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Deepak Nibade
2016-04-18 13:54:31 +05:30
committed by Terje Bergstrom
parent b63c4bced5
commit 2b2f84219c
4 changed files with 152 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/nvgpu/gk20a/hw_ctxsw_prog_gk20a.h
View File

@@ -62,6 +62,10 @@ static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014;
@@ -246,10 +250,6 @@ static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(v
{
return 0x0;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000ac;

72
drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
View File

@@ -938,10 +938,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
{
return (v & 0x1) << 18;
}
static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 gr_fecs_host_int_clear_r(void)
{
return 0x00409c20;
}
static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
{
return 0x2;
}
static inline u32 gr_fecs_host_int_enable_r(void)
{
return 0x00409c24;
@@ -3102,6 +3114,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
{
return 0x8;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
{
return 0x40000000;
@@ -3186,6 +3206,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(
{
return 0x40;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
{
return 0x1;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
{
return 0x2;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
{
return 0x4;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
{
return 0x8;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
{
return 0x00504650;
@@ -3202,6 +3242,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(
{
return 0x40;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
{
return 0x1;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
{
return 0x2;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
{
return 0x4;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
{
return 0x8;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
{
return 0x00504224;
@@ -3618,6 +3678,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
{
return 0x1 << 3;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
{
return 0x8;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
{
return 0x1 << 30;

8
drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
View File

@@ -74,6 +74,10 @@ static inline u32 ctxsw_prog_main_image_patch_count_o(void)
{
return 0x00000010;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0;
}
static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
{
return 0x00000014;
@@ -458,8 +462,4 @@ static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f
{
return 0x1;
}
static inline u32 ctxsw_prog_main_image_context_id_o(void)
{
return 0x000000f0;
}
#endif

72
drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
View File

@@ -954,10 +954,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
{
return (v & 0x1) << 18;
}
static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 gr_fecs_host_int_clear_r(void)
{
return 0x00409c20;
}
static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
{
return (v & 0x1) << 1;
}
static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
{
return 0x2;
}
static inline u32 gr_fecs_host_int_enable_r(void)
{
return 0x00409c24;
@@ -3138,6 +3150,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
{
return 0x8;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
{
return 0x40000000;
@@ -3234,6 +3254,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(
{
return 0x40;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
{
return 0x1;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
{
return 0x2;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
{
return 0x4;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
{
return 0x8;
}
static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
{
return 0x00504650;
@@ -3250,6 +3290,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(
{
return 0x40;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
{
return 0x1;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
{
return 0x2;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
{
return 0x4;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
{
return 0x8;
}
static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
{
return 0x80000000;
}
static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
{
return 0x00504224;
@@ -3694,6 +3754,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
{
return 0x1 << 3;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
{
return 0x8;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
{
return 0x0;
}
static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
{
return 0x1 << 30;