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gpu: nvgpu: mc: cleanup SWVR traceability

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Cleanup issues with traceability for common.mc:
- Move these declarations under macros or @cond as they are either
  non-fusa or private functions to the unit:
  - gm20b_mc_is_enabled
  - mc_gp10b_log_pending_intrs
  - mc_gp10b_ltc_isr
  - gv11b_mc_is_intr_hub_pending
- Fix typo in SWUTS for gv11b_mc_is_stall_and_eng_intr_pending

JIRA NVGPU-4818

Change-Id: I53a332627772e4d793430159ac1924c8f9ce8c1c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2280640
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Philip Elcan
2020-01-17 10:22:09 -05:00
committed by Alex Waterman
parent e195c05bcf
commit 2b86f65477
4 changed files with 16 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/nvgpu/hal/mc/mc_gm20b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -39,7 +39,9 @@ void gm20b_mc_enable(struct gk20a *g, u32 units);
void gm20b_mc_disable(struct gk20a *g, u32 units);
void gm20b_mc_reset(struct gk20a *g, u32 units);
u32 gm20b_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit);
#ifdef CONFIG_NVGPU_LS_PMU
bool gm20b_mc_is_enabled(struct gk20a *g, enum nvgpu_unit unit);
#endif
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_mc_intr_mask(struct gk20a *g);

7
drivers/gpu/nvgpu/hal/mc/mc_gp10b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -37,13 +37,18 @@ void mc_gp10b_isr_stall(struct gk20a *g);
bool mc_gp10b_is_intr1_pending(struct gk20a *g,
enum nvgpu_unit unit, u32 mc_intr_1);
#ifdef CONFIG_NVGPU_NON_FUSA
void mc_gp10b_log_pending_intrs(struct gk20a *g);
#endif
u32 mc_gp10b_intr_stall(struct gk20a *g);
void mc_gp10b_intr_stall_pause(struct gk20a *g);
void mc_gp10b_intr_stall_resume(struct gk20a *g);
u32 mc_gp10b_intr_nonstall(struct gk20a *g);
void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
void mc_gp10b_ltc_isr(struct gk20a *g);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#endif

7
drivers/gpu/nvgpu/hal/mc/mc_gv11b.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -27,9 +27,12 @@
struct gk20a;
bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
bool gv11b_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
u32 *eng_intr_pending);
bool gv11b_mc_is_mmu_fault_pending(struct gk20a *g);
/** @cond DOXYGEN_SHOULD_SKIP_THIS */
bool gv11b_mc_is_intr_hub_pending(struct gk20a *g, u32 mc_intr_0);
/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
#endif

3
userspace/units/mc/nvgpu-mc.h
View File

@@ -176,7 +176,8 @@ int test_intr_stall(struct unit_module *m, struct gk20a *g, void *args);
*
* Test Type: Feature
*
* Targets: gops_mc.is_stall_and_eng_intr_pending, mc_gp10b_is_intr1_pending
* Targets: gops_mc.is_stall_and_eng_intr_pending,
* gv11b_mc_is_stall_and_eng_intr_pending
*
* Input: test_setup_env must have been run.
*