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gpu: nvgpu: PMU PG interface headers reorg
Moved Power Gating (PG) interface from pmu_api.h & pmu_gk20a.h to gpmuif_ap/pg header files. gpmuif_pg.h - PMU Command/Message Interfaces for power gating (PG) gpmuif_ap.h - PMU Command/Message Interfaces for Adaptive Power Jira NVGPU-19 Change-Id: I1eeee78bdf89d894f9a4731435cdb121f73b1e0f Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1297203 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
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@@ -17,253 +17,6 @@
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#include <nvgpu/flcnif_cmn.h>
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#include "pmuif/gpmuif_pg_rppg.h"
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/* PMU Command/Message Interfaces for Adaptive Power */
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/* Macro to get Histogram index */
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#define PMU_AP_HISTOGRAM(idx) (idx)
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#define PMU_AP_HISTOGRAM_CONT (4)
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/* Total number of histogram bins */
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#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
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/* Mapping between Idle counters and histograms */
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#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
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#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
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#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
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#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
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/* Mapping between AP_CTRLs and Histograms */
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#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
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/* Mapping between AP_CTRLs and Idle counters */
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#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
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/* Adaptive Power Controls (AP_CTRL) */
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enum {
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PMU_AP_CTRL_ID_GRAPHICS = 0x0,
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PMU_AP_CTRL_ID_MAX,
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};
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/* AP_CTRL Statistics */
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struct pmu_ap_ctrl_stat {
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/*
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* Represents whether AP is active or not
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*/
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u8 b_active;
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/* Idle filter represented by histogram bin index */
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u8 idle_filter_x;
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u8 rsvd[2];
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/* Total predicted power saving cycles. */
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s32 power_saving_h_cycles;
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/* Counts how many times AP gave us -ve power benefits. */
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u32 bad_decision_count;
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/*
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* Number of times ap structure needs to skip AP iterations
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* KICK_CTRL from kernel updates this parameter.
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*/
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u32 skip_count;
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u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
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};
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/* Parameters initialized by INITn APCTRL command */
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struct pmu_ap_ctrl_init_params {
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/* Minimum idle filter value in Us */
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u32 min_idle_filter_us;
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/*
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* Minimum Targeted Saving in Us. AP will update idle thresholds only
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* if power saving achieved by updating idle thresholds is greater than
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* Minimum targeted saving.
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*/
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u32 min_target_saving_us;
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/* Minimum targeted residency of power feature in Us */
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u32 power_break_even_us;
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/*
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* Maximum number of allowed power feature cycles per sample.
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*
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* We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
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* AKA pgPerSampleMax in original algorithm.
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*/
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u32 cycles_per_sample_max;
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};
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/* AP Commands/Message structures */
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/*
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* Structure for Generic AP Commands
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*/
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struct pmu_ap_cmd_common {
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u8 cmd_type;
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u16 cmd_id;
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};
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/*
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* Structure for INIT AP command
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*/
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struct pmu_ap_cmd_init {
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u8 cmd_type;
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u16 cmd_id;
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u8 rsvd;
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u32 pg_sampling_period_us;
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};
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/*
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* Structure for Enable/Disable ApCtrl Commands
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*/
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struct pmu_ap_cmd_enable_ctrl {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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};
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struct pmu_ap_cmd_disable_ctrl {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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};
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/*
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* Structure for INIT command
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*/
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struct pmu_ap_cmd_init_ctrl {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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struct pmu_ap_ctrl_init_params params;
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};
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struct pmu_ap_cmd_init_and_enable_ctrl {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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struct pmu_ap_ctrl_init_params params;
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};
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/*
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* Structure for KICK_CTRL command
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*/
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struct pmu_ap_cmd_kick_ctrl {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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u32 skip_count;
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};
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/*
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* Structure for PARAM command
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*/
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struct pmu_ap_cmd_param {
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u8 cmd_type;
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u16 cmd_id;
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u8 ctrl_id;
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u32 data;
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};
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/*
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* Defines for AP commands
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*/
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enum {
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PMU_AP_CMD_ID_INIT = 0x0,
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PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
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PMU_AP_CMD_ID_ENABLE_CTRL,
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PMU_AP_CMD_ID_DISABLE_CTRL,
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PMU_AP_CMD_ID_KICK_CTRL,
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};
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/*
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* AP Command
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*/
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union pmu_ap_cmd {
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u8 cmd_type;
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struct pmu_ap_cmd_common cmn;
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struct pmu_ap_cmd_init init;
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struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
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struct pmu_ap_cmd_enable_ctrl enable_ctrl;
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struct pmu_ap_cmd_disable_ctrl disable_ctrl;
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struct pmu_ap_cmd_kick_ctrl kick_ctrl;
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};
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/*
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* Structure for generic AP Message
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*/
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struct pmu_ap_msg_common {
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u8 msg_type;
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u16 msg_id;
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};
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/*
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* Structure for INIT_ACK Message
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*/
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struct pmu_ap_msg_init_ack {
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u8 msg_type;
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u16 msg_id;
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u8 ctrl_id;
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u32 stats_dmem_offset;
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};
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/*
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* Defines for AP messages
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*/
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enum {
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PMU_AP_MSG_ID_INIT_ACK = 0x0,
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};
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/*
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* AP Message
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*/
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union pmu_ap_msg {
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u8 msg_type;
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struct pmu_ap_msg_common cmn;
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struct pmu_ap_msg_init_ack init_ack;
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};
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/* Default Sampling Period of AELPG */
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#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
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/* Default values of APCTRL parameters */
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#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
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#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
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#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
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#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
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/*
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* Disable reason for Adaptive Power Controller
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*/
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enum {
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APCTRL_DISABLE_REASON_RM_UNLOAD,
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APCTRL_DISABLE_REASON_RMCTRL,
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};
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/*
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* Adaptive Power Controller
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*/
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struct ap_ctrl {
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u32 stats_dmem_offset;
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u32 disable_reason_mask;
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struct pmu_ap_ctrl_stat stat_cache;
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u8 b_ready;
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};
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/*
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* Adaptive Power structure
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*
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* ap structure provides generic infrastructure to make any power feature
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* adaptive.
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*/
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struct pmu_ap {
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u32 supported_mask;
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struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
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};
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/*---------------------------------------------------------*/
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/*perfmon task defines*/
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@@ -399,228 +152,6 @@ struct pmu_perfmon_msg {
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struct pmu_perfmon_msg_generic gen;
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};
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};
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/*---------------------------------------------------------*/
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/*ELPG/PG defines*/
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enum {
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PMU_PG_ELPG_MSG_INIT_ACK,
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PMU_PG_ELPG_MSG_DISALLOW_ACK,
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PMU_PG_ELPG_MSG_ALLOW_ACK,
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PMU_PG_ELPG_MSG_FREEZE_ACK,
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PMU_PG_ELPG_MSG_FREEZE_ABORT,
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PMU_PG_ELPG_MSG_UNFREEZE_ACK,
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};
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struct pmu_pg_msg_elpg_msg {
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u8 msg_type;
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u8 engine_id;
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u16 msg;
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};
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enum {
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PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
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};
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struct pmu_pg_msg_stat {
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u8 msg_type;
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u8 engine_id;
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u16 sub_msg_id;
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u32 data;
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};
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enum {
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PMU_PG_MSG_ENG_BUF_LOADED,
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PMU_PG_MSG_ENG_BUF_UNLOADED,
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PMU_PG_MSG_ENG_BUF_FAILED,
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};
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struct pmu_pg_msg_eng_buf_stat {
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u8 msg_type;
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u8 engine_id;
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u8 buf_idx;
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u8 status;
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};
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struct pmu_pg_msg {
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union {
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u8 msg_type;
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struct pmu_pg_msg_elpg_msg elpg_msg;
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struct pmu_pg_msg_stat stat;
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struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
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/* TBD: other pg messages */
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union pmu_ap_msg ap_msg;
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struct nv_pmu_rppg_msg rppg_msg;
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};
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};
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enum {
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PMU_PG_ELPG_CMD_INIT,
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PMU_PG_ELPG_CMD_DISALLOW,
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PMU_PG_ELPG_CMD_ALLOW,
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PMU_PG_ELPG_CMD_FREEZE,
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PMU_PG_ELPG_CMD_UNFREEZE,
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};
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enum {
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PMU_PG_CMD_ID_ELPG_CMD = 0,
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PMU_PG_CMD_ID_ENG_BUF_LOAD,
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PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
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PMU_PG_CMD_ID_PG_STAT,
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PMU_PG_CMD_ID_PG_LOG_INIT,
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PMU_PG_CMD_ID_PG_LOG_FLUSH,
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PMU_PG_CMD_ID_PG_PARAM,
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PMU_PG_CMD_ID_ELPG_INIT,
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PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
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PMU_PG_CMD_ID_ELPG_ABORT_POLL,
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PMU_PG_CMD_ID_ELPG_PWR_UP,
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PMU_PG_CMD_ID_ELPG_DISALLOW,
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PMU_PG_CMD_ID_ELPG_ALLOW,
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PMU_PG_CMD_ID_AP,
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RM_PMU_PG_CMD_ID_PSI,
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RM_PMU_PG_CMD_ID_CG,
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PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
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PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
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PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
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PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
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PMU_PMU_PG_CMD_ID_RPPG = 0x24,
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};
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struct pmu_pg_cmd_elpg_cmd {
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u8 cmd_type;
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u8 engine_id;
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u16 cmd;
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};
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struct pmu_pg_cmd_eng_buf_load_v0 {
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u8 cmd_type;
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u8 engine_id;
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u8 buf_idx;
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u8 pad;
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u16 buf_size;
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u32 dma_base;
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u8 dma_offset;
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u8 dma_idx;
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};
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struct pmu_pg_cmd_eng_buf_load_v1 {
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u8 cmd_type;
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u8 engine_id;
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u8 buf_idx;
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u8 pad;
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struct flcn_mem_desc {
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struct falc_u64 dma_addr;
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u16 dma_size;
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u8 dma_idx;
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} dma_desc;
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};
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struct pmu_pg_cmd_eng_buf_load_v2 {
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u8 cmd_type;
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u8 engine_id;
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u8 buf_idx;
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u8 pad;
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struct flcn_mem_desc_v0 dma_desc;
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};
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enum {
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PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
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};
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#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
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#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01
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#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04
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#define PMU_PG_PARAM_CMD_POST_INIT 0x06
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#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
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#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
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#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3)
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#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3)
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#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
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( \
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NVGPU_PMU_GR_FEATURE_MASK_RPPG \
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)
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#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0)
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#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1)
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#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8)
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#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5)
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#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
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( \
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NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
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NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
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NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
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NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
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)
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#define PG_REQUEST_TYPE_GLOBAL 0x0
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#define PG_REQUEST_TYPE_PSTATE 0x1
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struct pmu_pg_cmd_gr_init_param {
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u8 cmd_type;
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u16 sub_cmd_id;
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u8 featuremask;
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};
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struct pmu_pg_cmd_ms_init_param {
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u8 cmd_type;
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u16 cmd_id;
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u8 psi;
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u8 idle_flipped_test_enabled;
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u16 psiSettleTimeUs;
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u8 rsvd[2];
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u32 support_mask;
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u32 abort_timeout_us;
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};
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struct pmu_pg_cmd_mclk_change {
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u8 cmd_type;
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u16 cmd_id;
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u8 rsvd;
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u32 data;
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};
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#define PG_VOLT_RAIL_IDX_MAX 2
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struct pmu_pg_volt_rail {
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u8 volt_rail_idx;
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u8 sleep_volt_dev_idx;
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u8 sleep_vfe_idx;
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u32 sleep_voltage_uv;
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u32 therm_vid0_cache;
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u32 therm_vid1_cache;
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};
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struct pmu_pg_cmd_post_init_param {
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u8 cmd_type;
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u16 cmd_id;
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struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
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};
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struct pmu_pg_cmd_stat {
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u8 cmd_type;
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u8 engine_id;
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u16 sub_cmd_id;
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u32 data;
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};
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struct pmu_pg_cmd {
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union {
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u8 cmd_type;
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struct pmu_pg_cmd_elpg_cmd elpg_cmd;
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struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
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struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
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struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
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struct pmu_pg_cmd_stat stat;
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struct pmu_pg_cmd_gr_init_param gr_init_param;
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struct pmu_pg_cmd_ms_init_param ms_init_param;
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struct pmu_pg_cmd_mclk_change mclk_change;
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struct pmu_pg_cmd_post_init_param post_init;
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/* TBD: other pg commands */
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union pmu_ap_cmd ap_cmd;
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struct nv_pmu_rppg_cmd rppg_cmd;
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};
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};
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||||
|
||||
/*---------------------------------------------------------*/
|
||||
/* ACR Commands/Message structures */
|
||||
|
||||
@@ -261,6 +261,7 @@ struct pmu_sequence {
|
||||
void* cb_params;
|
||||
};
|
||||
|
||||
/*PG defines used by nvpgu-pmu*/
|
||||
struct pmu_pg_stats_data {
|
||||
u32 gating_cnt;
|
||||
u32 ingating_time;
|
||||
@@ -269,79 +270,12 @@ struct pmu_pg_stats_data {
|
||||
u32 avg_exit_latency_us;
|
||||
};
|
||||
|
||||
struct pmu_pg_stats_v2 {
|
||||
u32 entry_count;
|
||||
u32 exit_count;
|
||||
u32 abort_count;
|
||||
u32 detection_count;
|
||||
u32 prevention_activate_count;
|
||||
u32 prevention_deactivate_count;
|
||||
u32 powered_up_time_us;
|
||||
u32 entry_latency_us;
|
||||
u32 exit_latency_us;
|
||||
u32 resident_time_us;
|
||||
u32 entry_latency_avg_us;
|
||||
u32 exit_latency_avg_us;
|
||||
u32 entry_latency_max_us;
|
||||
u32 exit_latency_max_us;
|
||||
u32 total_sleep_time_us;
|
||||
u32 total_non_sleep_time_us;
|
||||
};
|
||||
|
||||
struct pmu_pg_stats_v1 {
|
||||
/* Number of time PMU successfully engaged sleep state */
|
||||
u32 entry_count;
|
||||
/* Number of time PMU exit sleep state */
|
||||
u32 exit_count;
|
||||
/* Number of time PMU aborted in entry sequence */
|
||||
u32 abort_count;
|
||||
/*
|
||||
* Time for which GPU was neither in Sleep state not
|
||||
* executing sleep sequence.
|
||||
* */
|
||||
u32 poweredup_timeus;
|
||||
/* Entry and exit latency of current sleep cycle */
|
||||
u32 entry_latency_us;
|
||||
u32 exitlatencyus;
|
||||
/* Resident time for current sleep cycle. */
|
||||
u32 resident_timeus;
|
||||
/* Rolling average entry and exit latencies */
|
||||
u32 entrylatency_avgus;
|
||||
u32 exitlatency_avgus;
|
||||
/* Max entry and exit latencies */
|
||||
u32 entrylatency_maxus;
|
||||
u32 exitlatency_maxus;
|
||||
/* Total time spent in sleep and non-sleep state */
|
||||
u32 total_sleep_timeus;
|
||||
u32 total_nonsleep_timeus;
|
||||
};
|
||||
|
||||
struct pmu_pg_stats {
|
||||
u64 pg_entry_start_timestamp;
|
||||
u64 pg_ingating_start_timestamp;
|
||||
u64 pg_exit_start_timestamp;
|
||||
u64 pg_ungating_start_timestamp;
|
||||
u32 pg_avg_entry_time_us;
|
||||
u32 pg_ingating_cnt;
|
||||
u32 pg_ingating_time_us;
|
||||
u32 pg_avg_exit_time_us;
|
||||
u32 pg_ungating_count;
|
||||
u32 pg_ungating_time_us;
|
||||
u32 pg_gating_cnt;
|
||||
u32 pg_gating_deny_cnt;
|
||||
};
|
||||
|
||||
#define PMU_PG_IDLE_THRESHOLD_SIM 1000
|
||||
#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000
|
||||
/* TBD: QT or else ? */
|
||||
#define PMU_PG_IDLE_THRESHOLD 15000
|
||||
#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000
|
||||
|
||||
#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
|
||||
#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004)
|
||||
#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
|
||||
#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
|
||||
|
||||
#define PMU_PG_LPWR_FEATURE_RPPG 0x0
|
||||
#define PMU_PG_LPWR_FEATURE_MSCG 0x1
|
||||
|
||||
@@ -355,9 +289,22 @@ struct pmu_pg_stats {
|
||||
#define PMU_ELPG_STAT_OFF_ON_PENDING 4 /* elpg is off, caller has requested on, but ALLOW
|
||||
cmd hasn't been sent due to ENABLE_ALLOW delay */
|
||||
|
||||
#define PG_REQUEST_TYPE_GLOBAL 0x0
|
||||
#define PG_REQUEST_TYPE_PSTATE 0x1
|
||||
|
||||
#define PMU_MSCG_DISABLED 0
|
||||
#define PMU_MSCG_ENABLED 1
|
||||
|
||||
/* Default Sampling Period of AELPG */
|
||||
#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
|
||||
|
||||
/* Default values of APCTRL parameters */
|
||||
#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
|
||||
#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
|
||||
#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
|
||||
#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
|
||||
/*PG defines used by nvpgu-pmu*/
|
||||
|
||||
/* Falcon Register index */
|
||||
#define PMU_FALCON_REG_R0 (0)
|
||||
#define PMU_FALCON_REG_R1 (1)
|
||||
|
||||
247
drivers/gpu/nvgpu/pmuif/gpmuif_ap.h
Normal file
247
drivers/gpu/nvgpu/pmuif/gpmuif_ap.h
Normal file
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
#ifndef _GPMUIFAP_H_
|
||||
#define _GPMUIFAP_H_
|
||||
|
||||
/* PMU Command/Message Interfaces for Adaptive Power */
|
||||
/* Macro to get Histogram index */
|
||||
#define PMU_AP_HISTOGRAM(idx) (idx)
|
||||
#define PMU_AP_HISTOGRAM_CONT (4)
|
||||
|
||||
/* Total number of histogram bins */
|
||||
#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
|
||||
|
||||
/* Mapping between Idle counters and histograms */
|
||||
#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
|
||||
#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
|
||||
#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
|
||||
#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
|
||||
|
||||
|
||||
/* Mapping between AP_CTRLs and Histograms */
|
||||
#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
|
||||
|
||||
/* Mapping between AP_CTRLs and Idle counters */
|
||||
#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
|
||||
|
||||
/* Adaptive Power Controls (AP_CTRL) */
|
||||
enum {
|
||||
PMU_AP_CTRL_ID_GRAPHICS = 0x0,
|
||||
PMU_AP_CTRL_ID_MAX,
|
||||
};
|
||||
|
||||
/* AP_CTRL Statistics */
|
||||
struct pmu_ap_ctrl_stat {
|
||||
/*
|
||||
* Represents whether AP is active or not
|
||||
*/
|
||||
u8 b_active;
|
||||
|
||||
/* Idle filter represented by histogram bin index */
|
||||
u8 idle_filter_x;
|
||||
u8 rsvd[2];
|
||||
|
||||
/* Total predicted power saving cycles. */
|
||||
s32 power_saving_h_cycles;
|
||||
|
||||
/* Counts how many times AP gave us -ve power benefits. */
|
||||
u32 bad_decision_count;
|
||||
|
||||
/*
|
||||
* Number of times ap structure needs to skip AP iterations
|
||||
* KICK_CTRL from kernel updates this parameter.
|
||||
*/
|
||||
u32 skip_count;
|
||||
u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
|
||||
};
|
||||
|
||||
/* Parameters initialized by INITn APCTRL command */
|
||||
struct pmu_ap_ctrl_init_params {
|
||||
/* Minimum idle filter value in Us */
|
||||
u32 min_idle_filter_us;
|
||||
|
||||
/*
|
||||
* Minimum Targeted Saving in Us. AP will update idle thresholds only
|
||||
* if power saving achieved by updating idle thresholds is greater than
|
||||
* Minimum targeted saving.
|
||||
*/
|
||||
u32 min_target_saving_us;
|
||||
|
||||
/* Minimum targeted residency of power feature in Us */
|
||||
u32 power_break_even_us;
|
||||
|
||||
/*
|
||||
* Maximum number of allowed power feature cycles per sample.
|
||||
*
|
||||
* We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
|
||||
* AKA pgPerSampleMax in original algorithm.
|
||||
*/
|
||||
u32 cycles_per_sample_max;
|
||||
};
|
||||
|
||||
/* AP Commands/Message structures */
|
||||
|
||||
/*
|
||||
* Structure for Generic AP Commands
|
||||
*/
|
||||
struct pmu_ap_cmd_common {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for INIT AP command
|
||||
*/
|
||||
struct pmu_ap_cmd_init {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 rsvd;
|
||||
u32 pg_sampling_period_us;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for Enable/Disable ApCtrl Commands
|
||||
*/
|
||||
struct pmu_ap_cmd_enable_ctrl {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
|
||||
u8 ctrl_id;
|
||||
};
|
||||
|
||||
struct pmu_ap_cmd_disable_ctrl {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
|
||||
u8 ctrl_id;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for INIT command
|
||||
*/
|
||||
struct pmu_ap_cmd_init_ctrl {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 ctrl_id;
|
||||
struct pmu_ap_ctrl_init_params params;
|
||||
};
|
||||
|
||||
struct pmu_ap_cmd_init_and_enable_ctrl {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 ctrl_id;
|
||||
struct pmu_ap_ctrl_init_params params;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for KICK_CTRL command
|
||||
*/
|
||||
struct pmu_ap_cmd_kick_ctrl {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 ctrl_id;
|
||||
|
||||
u32 skip_count;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for PARAM command
|
||||
*/
|
||||
struct pmu_ap_cmd_param {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 ctrl_id;
|
||||
|
||||
u32 data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Defines for AP commands
|
||||
*/
|
||||
enum {
|
||||
PMU_AP_CMD_ID_INIT = 0x0,
|
||||
PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
|
||||
PMU_AP_CMD_ID_ENABLE_CTRL,
|
||||
PMU_AP_CMD_ID_DISABLE_CTRL,
|
||||
PMU_AP_CMD_ID_KICK_CTRL,
|
||||
};
|
||||
|
||||
/*
|
||||
* AP Command
|
||||
*/
|
||||
union pmu_ap_cmd {
|
||||
u8 cmd_type;
|
||||
struct pmu_ap_cmd_common cmn;
|
||||
struct pmu_ap_cmd_init init;
|
||||
struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
|
||||
struct pmu_ap_cmd_enable_ctrl enable_ctrl;
|
||||
struct pmu_ap_cmd_disable_ctrl disable_ctrl;
|
||||
struct pmu_ap_cmd_kick_ctrl kick_ctrl;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for generic AP Message
|
||||
*/
|
||||
struct pmu_ap_msg_common {
|
||||
u8 msg_type;
|
||||
u16 msg_id;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for INIT_ACK Message
|
||||
*/
|
||||
struct pmu_ap_msg_init_ack {
|
||||
u8 msg_type;
|
||||
u16 msg_id;
|
||||
u8 ctrl_id;
|
||||
u32 stats_dmem_offset;
|
||||
};
|
||||
|
||||
/*
|
||||
* Defines for AP messages
|
||||
*/
|
||||
enum {
|
||||
PMU_AP_MSG_ID_INIT_ACK = 0x0,
|
||||
};
|
||||
|
||||
/*
|
||||
* AP Message
|
||||
*/
|
||||
union pmu_ap_msg {
|
||||
u8 msg_type;
|
||||
struct pmu_ap_msg_common cmn;
|
||||
struct pmu_ap_msg_init_ack init_ack;
|
||||
};
|
||||
|
||||
/*
|
||||
* Adaptive Power Controller
|
||||
*/
|
||||
struct ap_ctrl {
|
||||
u32 stats_dmem_offset;
|
||||
u32 disable_reason_mask;
|
||||
struct pmu_ap_ctrl_stat stat_cache;
|
||||
u8 b_ready;
|
||||
};
|
||||
|
||||
/*
|
||||
* Adaptive Power structure
|
||||
*
|
||||
* ap structure provides generic infrastructure to make any power feature
|
||||
* adaptive.
|
||||
*/
|
||||
struct pmu_ap {
|
||||
u32 supported_mask;
|
||||
struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
|
||||
};
|
||||
|
||||
#endif /* _GPMUIFAP_H_*/
|
||||
311
drivers/gpu/nvgpu/pmuif/gpmuif_pg.h
Normal file
311
drivers/gpu/nvgpu/pmuif/gpmuif_pg.h
Normal file
@@ -0,0 +1,311 @@
|
||||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
#ifndef _GPMUIFPG_H_
|
||||
#define _GPMUIFPG_H_
|
||||
|
||||
#include "gpmuif_ap.h"
|
||||
#include "gpmuif_pg_rppg.h"
|
||||
|
||||
/*PG defines*/
|
||||
|
||||
/* Identifier for each PG */
|
||||
#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
|
||||
#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004)
|
||||
#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
|
||||
#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
|
||||
|
||||
/* PG message */
|
||||
enum {
|
||||
PMU_PG_ELPG_MSG_INIT_ACK,
|
||||
PMU_PG_ELPG_MSG_DISALLOW_ACK,
|
||||
PMU_PG_ELPG_MSG_ALLOW_ACK,
|
||||
PMU_PG_ELPG_MSG_FREEZE_ACK,
|
||||
PMU_PG_ELPG_MSG_FREEZE_ABORT,
|
||||
PMU_PG_ELPG_MSG_UNFREEZE_ACK,
|
||||
};
|
||||
|
||||
struct pmu_pg_msg_elpg_msg {
|
||||
u8 msg_type;
|
||||
u8 engine_id;
|
||||
u16 msg;
|
||||
};
|
||||
|
||||
enum {
|
||||
PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
|
||||
};
|
||||
|
||||
struct pmu_pg_msg_stat {
|
||||
u8 msg_type;
|
||||
u8 engine_id;
|
||||
u16 sub_msg_id;
|
||||
u32 data;
|
||||
};
|
||||
|
||||
enum {
|
||||
PMU_PG_MSG_ENG_BUF_LOADED,
|
||||
PMU_PG_MSG_ENG_BUF_UNLOADED,
|
||||
PMU_PG_MSG_ENG_BUF_FAILED,
|
||||
};
|
||||
|
||||
struct pmu_pg_msg_eng_buf_stat {
|
||||
u8 msg_type;
|
||||
u8 engine_id;
|
||||
u8 buf_idx;
|
||||
u8 status;
|
||||
};
|
||||
|
||||
struct pmu_pg_msg {
|
||||
union {
|
||||
u8 msg_type;
|
||||
struct pmu_pg_msg_elpg_msg elpg_msg;
|
||||
struct pmu_pg_msg_stat stat;
|
||||
struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
|
||||
/* TBD: other pg messages */
|
||||
union pmu_ap_msg ap_msg;
|
||||
struct nv_pmu_rppg_msg rppg_msg;
|
||||
};
|
||||
};
|
||||
|
||||
/* PG commands */
|
||||
enum {
|
||||
PMU_PG_ELPG_CMD_INIT,
|
||||
PMU_PG_ELPG_CMD_DISALLOW,
|
||||
PMU_PG_ELPG_CMD_ALLOW,
|
||||
PMU_PG_ELPG_CMD_FREEZE,
|
||||
PMU_PG_ELPG_CMD_UNFREEZE,
|
||||
};
|
||||
|
||||
enum {
|
||||
PMU_PG_CMD_ID_ELPG_CMD = 0,
|
||||
PMU_PG_CMD_ID_ENG_BUF_LOAD,
|
||||
PMU_PG_CMD_ID_ENG_BUF_UNLOAD,
|
||||
PMU_PG_CMD_ID_PG_STAT,
|
||||
PMU_PG_CMD_ID_PG_LOG_INIT,
|
||||
PMU_PG_CMD_ID_PG_LOG_FLUSH,
|
||||
PMU_PG_CMD_ID_PG_PARAM,
|
||||
PMU_PG_CMD_ID_ELPG_INIT,
|
||||
PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE,
|
||||
PMU_PG_CMD_ID_ELPG_ABORT_POLL,
|
||||
PMU_PG_CMD_ID_ELPG_PWR_UP,
|
||||
PMU_PG_CMD_ID_ELPG_DISALLOW,
|
||||
PMU_PG_CMD_ID_ELPG_ALLOW,
|
||||
PMU_PG_CMD_ID_AP,
|
||||
RM_PMU_PG_CMD_ID_PSI,
|
||||
RM_PMU_PG_CMD_ID_CG,
|
||||
PMU_PG_CMD_ID_ZBC_TABLE_UPDATE,
|
||||
PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20,
|
||||
PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE,
|
||||
PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE,
|
||||
PMU_PMU_PG_CMD_ID_RPPG = 0x24,
|
||||
};
|
||||
|
||||
enum {
|
||||
PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
|
||||
};
|
||||
|
||||
#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
|
||||
#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01
|
||||
#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04
|
||||
#define PMU_PG_PARAM_CMD_POST_INIT 0x06
|
||||
|
||||
#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
|
||||
#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
|
||||
#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3)
|
||||
|
||||
#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3)
|
||||
#define NVGPU_PMU_GR_FEATURE_MASK_ALL \
|
||||
( \
|
||||
NVGPU_PMU_GR_FEATURE_MASK_RPPG \
|
||||
)
|
||||
|
||||
#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0)
|
||||
#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1)
|
||||
#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8)
|
||||
#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5)
|
||||
|
||||
#define NVGPU_PMU_MS_FEATURE_MASK_ALL \
|
||||
( \
|
||||
NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\
|
||||
NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\
|
||||
NVGPU_PMU_MS_FEATURE_MASK_RPPG |\
|
||||
NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \
|
||||
)
|
||||
|
||||
|
||||
struct pmu_pg_cmd_elpg_cmd {
|
||||
u8 cmd_type;
|
||||
u8 engine_id;
|
||||
u16 cmd;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_eng_buf_load_v0 {
|
||||
u8 cmd_type;
|
||||
u8 engine_id;
|
||||
u8 buf_idx;
|
||||
u8 pad;
|
||||
u16 buf_size;
|
||||
u32 dma_base;
|
||||
u8 dma_offset;
|
||||
u8 dma_idx;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_eng_buf_load_v1 {
|
||||
u8 cmd_type;
|
||||
u8 engine_id;
|
||||
u8 buf_idx;
|
||||
u8 pad;
|
||||
struct flcn_mem_desc {
|
||||
struct falc_u64 dma_addr;
|
||||
u16 dma_size;
|
||||
u8 dma_idx;
|
||||
} dma_desc;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_eng_buf_load_v2 {
|
||||
u8 cmd_type;
|
||||
u8 engine_id;
|
||||
u8 buf_idx;
|
||||
u8 pad;
|
||||
struct flcn_mem_desc_v0 dma_desc;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_gr_init_param {
|
||||
u8 cmd_type;
|
||||
u16 sub_cmd_id;
|
||||
u8 featuremask;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_ms_init_param {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 psi;
|
||||
u8 idle_flipped_test_enabled;
|
||||
u16 psiSettleTimeUs;
|
||||
u8 rsvd[2];
|
||||
u32 support_mask;
|
||||
u32 abort_timeout_us;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_mclk_change {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
u8 rsvd;
|
||||
u32 data;
|
||||
};
|
||||
|
||||
#define PG_VOLT_RAIL_IDX_MAX 2
|
||||
|
||||
struct pmu_pg_volt_rail {
|
||||
u8 volt_rail_idx;
|
||||
u8 sleep_volt_dev_idx;
|
||||
u8 sleep_vfe_idx;
|
||||
u32 sleep_voltage_uv;
|
||||
u32 therm_vid0_cache;
|
||||
u32 therm_vid1_cache;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_post_init_param {
|
||||
u8 cmd_type;
|
||||
u16 cmd_id;
|
||||
struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX];
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd_stat {
|
||||
u8 cmd_type;
|
||||
u8 engine_id;
|
||||
u16 sub_cmd_id;
|
||||
u32 data;
|
||||
};
|
||||
|
||||
struct pmu_pg_cmd {
|
||||
union {
|
||||
u8 cmd_type;
|
||||
struct pmu_pg_cmd_elpg_cmd elpg_cmd;
|
||||
struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
|
||||
struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
|
||||
struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
|
||||
struct pmu_pg_cmd_stat stat;
|
||||
struct pmu_pg_cmd_gr_init_param gr_init_param;
|
||||
struct pmu_pg_cmd_ms_init_param ms_init_param;
|
||||
struct pmu_pg_cmd_mclk_change mclk_change;
|
||||
struct pmu_pg_cmd_post_init_param post_init;
|
||||
/* TBD: other pg commands */
|
||||
union pmu_ap_cmd ap_cmd;
|
||||
struct nv_pmu_rppg_cmd rppg_cmd;
|
||||
};
|
||||
};
|
||||
|
||||
/* Statistics structure for PG features */
|
||||
struct pmu_pg_stats_v2 {
|
||||
u32 entry_count;
|
||||
u32 exit_count;
|
||||
u32 abort_count;
|
||||
u32 detection_count;
|
||||
u32 prevention_activate_count;
|
||||
u32 prevention_deactivate_count;
|
||||
u32 powered_up_time_us;
|
||||
u32 entry_latency_us;
|
||||
u32 exit_latency_us;
|
||||
u32 resident_time_us;
|
||||
u32 entry_latency_avg_us;
|
||||
u32 exit_latency_avg_us;
|
||||
u32 entry_latency_max_us;
|
||||
u32 exit_latency_max_us;
|
||||
u32 total_sleep_time_us;
|
||||
u32 total_non_sleep_time_us;
|
||||
};
|
||||
|
||||
struct pmu_pg_stats_v1 {
|
||||
/* Number of time PMU successfully engaged sleep state */
|
||||
u32 entry_count;
|
||||
/* Number of time PMU exit sleep state */
|
||||
u32 exit_count;
|
||||
/* Number of time PMU aborted in entry sequence */
|
||||
u32 abort_count;
|
||||
/*
|
||||
* Time for which GPU was neither in Sleep state not
|
||||
* executing sleep sequence.
|
||||
*/
|
||||
u32 poweredup_timeus;
|
||||
/* Entry and exit latency of current sleep cycle */
|
||||
u32 entry_latency_us;
|
||||
u32 exitlatencyus;
|
||||
/* Resident time for current sleep cycle. */
|
||||
u32 resident_timeus;
|
||||
/* Rolling average entry and exit latencies */
|
||||
u32 entrylatency_avgus;
|
||||
u32 exitlatency_avgus;
|
||||
/* Max entry and exit latencies */
|
||||
u32 entrylatency_maxus;
|
||||
u32 exitlatency_maxus;
|
||||
/* Total time spent in sleep and non-sleep state */
|
||||
u32 total_sleep_timeus;
|
||||
u32 total_nonsleep_timeus;
|
||||
};
|
||||
|
||||
struct pmu_pg_stats {
|
||||
u64 pg_entry_start_timestamp;
|
||||
u64 pg_ingating_start_timestamp;
|
||||
u64 pg_exit_start_timestamp;
|
||||
u64 pg_ungating_start_timestamp;
|
||||
u32 pg_avg_entry_time_us;
|
||||
u32 pg_ingating_cnt;
|
||||
u32 pg_ingating_time_us;
|
||||
u32 pg_avg_exit_time_us;
|
||||
u32 pg_ungating_count;
|
||||
u32 pg_ungating_time_us;
|
||||
u32 pg_gating_cnt;
|
||||
u32 pg_gating_deny_cnt;
|
||||
};
|
||||
|
||||
#endif /* _GPMUIFPG_H_*/
|
||||
@@ -17,6 +17,8 @@
|
||||
#include <nvgpu/flcnif_cmn.h>
|
||||
#include "gpmuif_cmn.h"
|
||||
#include "gpmuif_pmu.h"
|
||||
#include "gpmuif_ap.h"
|
||||
#include "gpmuif_pg.h"
|
||||
#include "gpmuifboardobj.h"
|
||||
#include "gpmuifclk.h"
|
||||
#include "gpmuifperf.h"
|
||||
|
||||
Reference in New Issue
Block a user