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gpu: nvgpu: Use queried interrupt ids

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Change-Id: I258b54447d09b32adc076de50997d792f0567af5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/601019
Reviewed-by: Automatic_Commit_Validation_User
This commit is contained in:
Terje Bergstrom
2014-11-11 11:13:11 +02:00
committed by Deepak Nibade
parent 7918de1c1b
commit 2d23236ae2
2 changed files with 20 additions and 8 deletions
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8
drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h
View File

@@ -102,6 +102,14 @@ static inline u32 top_device_info_runlist_enum_v(u32 r)
{
return (r >> 21) & 0xf;
}
static inline u32 top_device_info_intr_enum_v(u32 r)
{
return (r >> 15) & 0x1f;
}
static inline u32 top_device_info_reset_enum_v(u32 r)
{
return (r >> 9) & 0x1f;
}
static inline u32 top_device_info_type_enum_v(u32 r)
{
return (r >> 2) & 0x1fffffff;

20
drivers/gpu/nvgpu/gp10b/mc_gp10b.c
View File

@@ -21,17 +21,19 @@
void mc_gp10b_intr_enable(struct gk20a *g)
{
u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff);
gk20a_writel(g, mc_intr_en_set_r(0),
mc_intr_pfifo_pending_f()
| mc_intr_pgraph_pending_f());
| eng_intr_mask);
gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff);
gk20a_writel(g, mc_intr_en_set_r(1),
mc_intr_pfifo_pending_f()
| mc_intr_pgraph_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f());
| mc_intr_pbus_pending_f()
| eng_intr_mask);
}
irqreturn_t mc_gp10b_isr_stall(struct gk20a *g)
@@ -71,6 +73,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g)
irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
{
u32 mc_intr_0;
u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
@@ -78,7 +81,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
if (mc_intr_0 & mc_intr_pgraph_pending_f())
if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
if (mc_intr_0 & mc_intr_pfifo_pending_f())
gk20a_fifo_isr(g);
@@ -93,7 +96,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
gk20a_writel(g, mc_intr_en_set_r(0),
mc_intr_pfifo_pending_f()
| mc_intr_pgraph_pending_f());
| eng_intr_mask);
return IRQ_HANDLED;
}
@@ -101,6 +104,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g)
irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
{
u32 mc_intr_1;
u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g);
gk20a_dbg(gpu_dbg_intr, "interrupt thread launched");
@@ -110,15 +114,15 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g)
if (mc_intr_1 & mc_intr_pfifo_pending_f())
gk20a_fifo_nonstall_isr(g);
if (mc_intr_1 & mc_intr_pgraph_pending_f())
if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
gk20a_gr_nonstall_isr(g);
gk20a_writel(g, mc_intr_en_set_r(1),
mc_intr_pfifo_pending_f()
| mc_intr_pgraph_pending_f()
| mc_intr_priv_ring_pending_f()
| mc_intr_ltc_pending_f()
| mc_intr_pbus_pending_f());
| mc_intr_pbus_pending_f()
| eng_intr_mask);
return IRQ_HANDLED;
}