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Revert "gpu: nvgpu: FBQ data struct to support FBQ implementation"

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This reverts commit 92ebb4d245.

Bug 2487534

Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Change-Id: Ic8db42d2da47284c00b23c786830176b7a2dfe18
Reviewed-on: https://git-master.nvidia.com/r/2001922
This commit is contained in:
Konsta Holtta
2019-01-23 15:47:05 +02:00
parent 0aeb2a6f87
commit 2d496942c5
5 changed files with 5 additions and 76 deletions
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1
drivers/gpu/nvgpu/common/pmu/pmu.c
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@@ -24,7 +24,6 @@
#include <nvgpu/dma.h>
#include <nvgpu/log.h>
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
#include <nvgpu/pmuif/gpmu_super_surf_if.h>
#include <nvgpu/enabled.h>
#include <nvgpu/barrier.h>
#include <nvgpu/timers.h>

3
drivers/gpu/nvgpu/include/nvgpu/boardobjgrp.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -34,7 +34,6 @@ struct pmu_surface;
#include <nvgpu/boardobjgrpmask.h>
#include <nvgpu/list.h>
#include <nvgpu/pmu.h>
#include <nvgpu/pmuif/gpmu_super_surf_if.h>
/*
* Board Object Group destructor.

15
drivers/gpu/nvgpu/include/nvgpu/flcnif_cmn.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -118,17 +118,4 @@ typedef u8 flcn_status;
#define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2U)) / (b))
/* FB queue support interfaces */
/* Header for a FBQ qntry */
struct nv_falcon_fbq_hdr {
/* Element this CMD will use in the FB CMD Q. */
u8 element_index;
/* Pad bytes to keep 4 byte alignment. */
u8 padding[3];
/* Size of allocation in nvgpu managed heap. */
u16 heap_size;
/* Heap location this CMD will use in the nvgpu managed heap. */
u16 heap_offset;
};
#endif /* NVGPU_FLCNIF_CMN_H */

10
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -22,8 +22,6 @@
#ifndef NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
#define NVGPU_PMUIF_GPMU_SUPER_SURF_IF_H
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
struct nv_pmu_super_surface_hdr {
u32 memberMask;
u16 dmemBufferSizeMax;
@@ -37,12 +35,6 @@ NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_super_surface_hdr,
* NOTE: Any new substructures or entries must be aligned.
*/
struct nv_pmu_super_surface {
struct {
struct nv_pmu_fbq_cmd_queues cmd_queues;
struct nv_pmu_fbq_msg_queue msg_queue;
} fbq;
union nv_pmu_super_surface_hdr_aligned hdr;
struct {

52
drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,7 @@
#include "gpmuiftherm.h"
#include "gpmuifthermsensor.h"
#include "gpmuifseq.h"
#include "gpmu_super_surf_if.h"
/*
* Command requesting execution of the RPC (Remote Procedure Call)
@@ -139,53 +140,4 @@ struct pmu_msg {
#define PMU_UNIT_ID_IS_VALID(id) \
(((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))
/*
* PMU Command structures for FB queue
*/
/* Size of a single element in the CMD queue. */
#define NV_PMU_FBQ_CMD_ELEMENT_SIZE 2048U
/* Number of elements in each queue. */
#define NV_PMU_FBQ_CMD_NUM_ELEMENTS 16U
/* Total number of CMD queues. */
#define NV_PMU_FBQ_CMD_COUNT 2U
/* Size of a single element in the MSG queue. */
#define NV_PMU_FBQ_MSG_ELEMENT_SIZE 64U
/* Number of elements in each queue. */
#define NV_PMU_FBQ_MSG_NUM_ELEMENTS 16U
/* Single MSG (response) queue. */
#define NV_PMU_FBQ_MSG_COUNT 1U
/* structure for a single PMU FB CMD queue entry */
struct nv_pmu_fbq_cmd_q_element {
struct nv_falcon_fbq_hdr fbq_hdr;
u8 data[NV_PMU_FBQ_CMD_ELEMENT_SIZE -
sizeof(struct nv_falcon_fbq_hdr)];
};
/* structure for a single PMU FB MSG queue entry */
struct nv_pmu_fbq_msg_q_element {
u8 data[NV_PMU_FBQ_MSG_ELEMENT_SIZE];
};
/* structure for a single FB CMD queue */
struct nv_pmu_fbq_cmd_queue {
struct nv_pmu_fbq_cmd_q_element element[NV_PMU_FBQ_CMD_NUM_ELEMENTS];
};
/* structure for a set of FB CMD queue */
struct nv_pmu_fbq_cmd_queues {
struct nv_pmu_fbq_cmd_queue queue[NV_PMU_FBQ_CMD_COUNT];
};
/* structure for a single FB MSG queue */
struct nv_pmu_fbq_msg_queue {
struct nv_pmu_fbq_msg_q_element element[NV_PMU_FBQ_MSG_NUM_ELEMENTS];
};
#endif /* NVGPU_PMUIF_NVGPU_GPMU_CMDIF_H*/