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gpu: nvgpu: move ramfc capture to ramfc

Browse Source 
Replaced the following hal
- fifo.capture_channel_ram_dump

With
- ramfc.capture_ram_dump

This HAL captures all fields in ramfc. It no longer
reads hw_state (this has to be done from common code).

Jira NVGPU-1750

Change-Id: I92ee58a7a90fbd0b155acf66b1b6ff22a8e3259e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075939
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-03-18 14:47:42 -07:00
committed by mobile promotions
parent 6009662fa5
commit 2e68f784b0
16 changed files with 87 additions and 89 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/common/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -424,7 +424,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.init_engine_info = vgpu_fifo_init_engine_info,
.get_engines_mask_on_id = NULL,
.dump_channel_status_ramfc = NULL,
.capture_channel_ram_dump = NULL,
.is_preempt_pending = NULL,
.reset_enable_hw = NULL,
.teardown_ch_tsg = NULL,
@@ -486,6 +485,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
},
.ramfc = {
.setup = vgpu_ramfc_setup,
.capture_ram_dump = NULL,
.commit_userd = NULL,
.get_syncpt = NULL,
.set_syncpt = NULL,

2
drivers/gpu/nvgpu/common/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -497,7 +497,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.init_engine_info = vgpu_fifo_init_engine_info,
.get_engines_mask_on_id = NULL,
.dump_channel_status_ramfc = NULL,
.capture_channel_ram_dump = NULL,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
.reset_enable_hw = NULL,
.teardown_ch_tsg = NULL,
@@ -566,6 +565,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
},
.ramfc = {
.setup = vgpu_ramfc_setup,
.capture_ram_dump = NULL,
.commit_userd = NULL,
.get_syncpt = NULL,
.set_syncpt = NULL,

41
drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
View File

@@ -1556,44 +1556,6 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index)
}
}
void gk20a_capture_channel_ram_dump(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
g->ops.channel.read_state(g, ch, &info->hw_state);
info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_top_level_get_w(),
ram_fc_pb_top_level_get_hi_w());
info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_put_w(),
ram_fc_pb_put_hi_w());
info->inst.pb_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_get_w(),
ram_fc_pb_get_hi_w());
info->inst.pb_fetch = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_fetch_w(),
ram_fc_pb_fetch_hi_w());
info->inst.pb_header = nvgpu_mem_rd32(g, mem,
ram_fc_pb_header_w());
info->inst.pb_count = nvgpu_mem_rd32(g, mem,
ram_fc_pb_count_w());
info->inst.syncpointa = nvgpu_mem_rd32(g, mem,
ram_fc_syncpointa_w());
info->inst.syncpointb = nvgpu_mem_rd32(g, mem,
ram_fc_syncpointb_w());
info->inst.semaphorea = nvgpu_mem_rd32(g, mem,
ram_fc_semaphorea_w());
info->inst.semaphoreb = nvgpu_mem_rd32(g, mem,
ram_fc_semaphoreb_w());
info->inst.semaphorec = nvgpu_mem_rd32(g, mem,
ram_fc_semaphorec_w());
info->inst.semaphored = nvgpu_mem_rd32(g, mem,
ram_fc_semaphored_w());
}
void gk20a_dump_channel_status_ramfc(struct gk20a *g,
struct gk20a_debug_output *o,
struct nvgpu_channel_dump_info *info)
@@ -1713,7 +1675,8 @@ void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
info->sema.addr = nvgpu_hw_semaphore_addr(hw_sema);
}
g->ops.fifo.capture_channel_ram_dump(g, ch, info);
g->ops.channel.read_state(g, ch, &info->hw_state);
g->ops.ramfc.capture_ram_dump(g, ch, info);
gk20a_channel_put(ch);
}

3
drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
View File

@@ -311,9 +311,6 @@ static inline void gk20a_fifo_profile_snapshot(
void gk20a_dump_channel_status_ramfc(struct gk20a *g,
struct gk20a_debug_output *o,
struct nvgpu_channel_dump_info *info);
void gk20a_capture_channel_ram_dump(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
void gk20a_debug_dump_all_channel_status_ramfc(struct gk20a *g,
struct gk20a_debug_output *o);
const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index);

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -577,7 +577,6 @@ static const struct gpu_ops gm20b_ops = {
.init_engine_info = gm20b_fifo_init_engine_info,
.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.capture_channel_ram_dump = gk20a_capture_channel_ram_dump,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
@@ -649,6 +648,7 @@ static const struct gpu_ops gm20b_ops = {
},
.ramfc = {
.setup = gk20a_ramfc_setup,
.capture_ram_dump = gk20a_ramfc_capture_ram_dump,
.commit_userd = gk20a_ramfc_commit_userd,
.get_syncpt = NULL,
.set_syncpt = NULL,

3
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -62,6 +62,7 @@
#include "hal/fifo/engines_gm20b.h"
#include "hal/fifo/engine_status_gm20b.h"
#include "hal/fifo/pbdma_status_gm20b.h"
#include "hal/fifo/ramfc_gk20a.h"
#include "hal/fifo/ramfc_gp10b.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/fifo_intr_gk20a.h"
@@ -656,7 +657,6 @@ static const struct gpu_ops gp10b_ops = {
.init_engine_info = gm20b_fifo_init_engine_info,
.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
.capture_channel_ram_dump = gk20a_capture_channel_ram_dump,
.is_preempt_pending = gk20a_fifo_is_preempt_pending,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
@@ -728,6 +728,7 @@ static const struct gpu_ops gp10b_ops = {
},
.ramfc = {
.setup = gp10b_ramfc_setup,
.capture_ram_dump = gk20a_ramfc_capture_ram_dump,
.commit_userd = gp10b_ramfc_commit_userd,
.get_syncpt = gp10b_ramfc_get_syncpt,
.set_syncpt = gp10b_ramfc_set_syncpt,

2
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -833,7 +833,6 @@ static const struct gpu_ops gv100_ops = {
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
.reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -912,6 +911,7 @@ static const struct gpu_ops gv100_ops = {
},
.ramfc = {
.setup = gv11b_ramfc_setup,
.capture_ram_dump = gv11b_ramfc_capture_ram_dump,
.commit_userd = gp10b_ramfc_commit_userd,
.get_syncpt = NULL,
.set_syncpt = NULL,

34
drivers/gpu/nvgpu/gv11b/fifo_gv11b.c
View File

@@ -93,40 +93,6 @@ void gv11b_ring_channel_doorbell(struct channel_gk20a *c)
usermode_notify_channel_pending_id_f(hw_chid));
}
void gv11b_capture_channel_ram_dump(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
g->ops.channel.read_state(g, ch, &info->hw_state);
info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_top_level_get_w(),
ram_fc_pb_top_level_get_hi_w());
info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_put_w(),
ram_fc_pb_put_hi_w());
info->inst.pb_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_get_w(),
ram_fc_pb_get_hi_w());
info->inst.pb_fetch = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_fetch_w(),
ram_fc_pb_fetch_hi_w());
info->inst.pb_header = nvgpu_mem_rd32(g, mem,
ram_fc_pb_header_w());
info->inst.pb_count = nvgpu_mem_rd32(g, mem,
ram_fc_pb_count_w());
info->inst.sem_addr = nvgpu_mem_rd32_pair(g, mem,
ram_fc_sem_addr_lo_w(),
ram_fc_sem_addr_hi_w());
info->inst.sem_payload = nvgpu_mem_rd32_pair(g, mem,
ram_fc_sem_payload_lo_w(),
ram_fc_sem_payload_hi_w());
info->inst.sem_execute = nvgpu_mem_rd32(g, mem,
ram_fc_sem_execute_w());
}
void gv11b_dump_channel_status_ramfc(struct gk20a *g,
struct gk20a_debug_output *o,
struct nvgpu_channel_dump_info *info)

3
drivers/gpu/nvgpu/gv11b/fifo_gv11b.h
View File

@@ -50,9 +50,6 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g,
void gv11b_dump_channel_status_ramfc(struct gk20a *g,
struct gk20a_debug_output *o,
struct nvgpu_channel_dump_info *info);
void gv11b_capture_channel_ram_dump(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id,
unsigned int id_type);
int gv11b_fifo_preempt_channel(struct gk20a *g, struct channel_gk20a *ch);

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -789,7 +789,6 @@ static const struct gpu_ops gv11b_ops = {
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
.reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -868,6 +867,7 @@ static const struct gpu_ops gv11b_ops = {
},
.ramfc = {
.setup = gv11b_ramfc_setup,
.capture_ram_dump = gv11b_ramfc_capture_ram_dump,
.commit_userd = gp10b_ramfc_commit_userd,
.get_syncpt = NULL,
.set_syncpt = NULL,

35
drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.c
View File

@@ -132,3 +132,38 @@ int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
return g->ops.ramfc.commit_userd(ch);
}
void gk20a_ramfc_capture_ram_dump(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_top_level_get_w(),
ram_fc_pb_top_level_get_hi_w());
info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_put_w(),
ram_fc_pb_put_hi_w());
info->inst.pb_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_get_w(),
ram_fc_pb_get_hi_w());
info->inst.pb_fetch = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_fetch_w(),
ram_fc_pb_fetch_hi_w());
info->inst.pb_header = nvgpu_mem_rd32(g, mem,
ram_fc_pb_header_w());
info->inst.pb_count = nvgpu_mem_rd32(g, mem,
ram_fc_pb_count_w());
info->inst.syncpointa = nvgpu_mem_rd32(g, mem,
ram_fc_syncpointa_w());
info->inst.syncpointb = nvgpu_mem_rd32(g, mem,
ram_fc_syncpointb_w());
info->inst.semaphorea = nvgpu_mem_rd32(g, mem,
ram_fc_semaphorea_w());
info->inst.semaphoreb = nvgpu_mem_rd32(g, mem,
ram_fc_semaphoreb_w());
info->inst.semaphorec = nvgpu_mem_rd32(g, mem,
ram_fc_semaphorec_w());
info->inst.semaphored = nvgpu_mem_rd32(g, mem,
ram_fc_semaphored_w());
}

3
drivers/gpu/nvgpu/hal/fifo/ramfc_gk20a.h
View File

@@ -25,9 +25,12 @@
#include <nvgpu/types.h>
struct channel_gk20a;
struct nvgpu_channel_dump_info;
int gk20a_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags);
int gk20a_ramfc_commit_userd(struct channel_gk20a *ch);
void gk20a_ramfc_capture_ram_dump(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
#endif /* NVGPU_RAMFC_GK20A_H */

31
drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.c
View File

@@ -115,3 +115,34 @@ int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
return g->ops.ramfc.commit_userd(ch);
}
void gv11b_ramfc_capture_ram_dump(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info)
{
struct nvgpu_mem *mem = &ch->inst_block;
info->inst.pb_top_level_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_top_level_get_w(),
ram_fc_pb_top_level_get_hi_w());
info->inst.pb_put = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_put_w(),
ram_fc_pb_put_hi_w());
info->inst.pb_get = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_get_w(),
ram_fc_pb_get_hi_w());
info->inst.pb_fetch = nvgpu_mem_rd32_pair(g, mem,
ram_fc_pb_fetch_w(),
ram_fc_pb_fetch_hi_w());
info->inst.pb_header = nvgpu_mem_rd32(g, mem,
ram_fc_pb_header_w());
info->inst.pb_count = nvgpu_mem_rd32(g, mem,
ram_fc_pb_count_w());
info->inst.sem_addr = nvgpu_mem_rd32_pair(g, mem,
ram_fc_sem_addr_lo_w(),
ram_fc_sem_addr_hi_w());
info->inst.sem_payload = nvgpu_mem_rd32_pair(g, mem,
ram_fc_sem_payload_lo_w(),
ram_fc_sem_payload_hi_w());
info->inst.sem_execute = nvgpu_mem_rd32(g, mem,
ram_fc_sem_execute_w());
}

4
drivers/gpu/nvgpu/hal/fifo/ramfc_gv11b.h
View File

@@ -25,9 +25,13 @@
#include <nvgpu/types.h>
struct gk20a;
struct channel_gk20a;
struct nvgpu_channel_dump_info;
int gv11b_ramfc_setup(struct channel_gk20a *ch, u64 gpfifo_base,
u32 gpfifo_entries, u64 pbdma_acquire_timeout, u32 flags);
void gv11b_ramfc_capture_ram_dump(struct gk20a *g, struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
#endif /* NVGPU_RAMFC_GV11B_H */

6
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -906,9 +906,6 @@ struct gpu_ops {
void (*dump_channel_status_ramfc)(struct gk20a *g,
struct gk20a_debug_output *o,
struct nvgpu_channel_dump_info *info);
void (*capture_channel_ram_dump)(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
int (*is_preempt_pending)(struct gk20a *g, u32 id,
unsigned int id_type);
int (*reset_enable_hw)(struct gk20a *g);
@@ -957,6 +954,9 @@ struct gpu_ops {
int (*setup)(struct channel_gk20a *ch, u64 gpfifo_base,
u32 gpfifo_entries, u64 pbdma_acquire_timeout,
u32 flags);
void (*capture_ram_dump)(struct gk20a *g,
struct channel_gk20a *ch,
struct nvgpu_channel_dump_info *info);
int (*commit_userd)(struct channel_gk20a *ch);
u32 (*get_syncpt)(struct channel_gk20a *ch);
void (*set_syncpt)(struct channel_gk20a *ch, u32 syncpt);

3
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -56,6 +56,7 @@
#include "hal/fifo/pbdma_tu104.h"
#include "hal/fifo/engines_gv11b.h"
#include "hal/fifo/ramfc_gp10b.h"
#include "hal/fifo/ramfc_gv11b.h"
#include "hal/fifo/ramfc_tu104.h"
#include "hal/fifo/userd_gk20a.h"
#include "hal/fifo/userd_gv11b.h"
@@ -868,7 +869,6 @@ static const struct gpu_ops tu104_ops = {
.init_pbdma_info = gk20a_fifo_init_pbdma_info,
.get_engines_mask_on_id = gk20a_fifo_engines_on_id,
.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc,
.capture_channel_ram_dump = gv11b_capture_channel_ram_dump,
.is_preempt_pending = gv11b_fifo_is_preempt_pending,
.reset_enable_hw = gv11b_init_fifo_reset_enable_hw,
.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg,
@@ -949,6 +949,7 @@ static const struct gpu_ops tu104_ops = {
},
.ramfc = {
.setup = tu104_ramfc_setup,
.capture_ram_dump = gv11b_ramfc_capture_ram_dump,
.commit_userd = gp10b_ramfc_commit_userd,
.get_syncpt = NULL,
.set_syncpt = NULL,