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gpu: nvgpu: Skip graphics CB programming for MIG

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Added logic to skip the following graphics CB allocation, map and
programming sequence when MIG is enabled.

Global CB:
1) NVGPU_GR_GLOBAL_CTX_CIRCULAR
2) NVGPU_GR_GLOBAL_CTX_PAGEPOOL
3) NVGPU_GR_GLOBAL_CTX_ATTRIBUTE
4) NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR
5) NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR
6) NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR
7) NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER

CTX CB:
1) NVGPU_GR_CTX_CIRCULAR_VA
2) NVGPU_GR_CTX_PAGEPOOL_VA
3) NVGPU_GR_CTX_ATTRIBUTE_VA
4) NVGPU_GR_CTX_RTV_CIRCULAR_BUFFER_VA

JIRA NVGPU-5650

Change-Id: I38c2859ce57ad76c58a772fdf9f589f2106149af
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2423450
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2020-10-05 13:38:53 +05:30
committed by Alex Waterman
parent c9a964aefd
commit 2ecb5feaad
9 changed files with 231 additions and 154 deletions
Download Patch File Download Diff File Expand all files Collapse all files

86
drivers/gpu/nvgpu/common/gr/global_ctx.c
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@@ -160,18 +160,26 @@ static int nvgpu_gr_global_ctx_buffer_alloc_vpr(struct gk20a *g,
static bool nvgpu_gr_global_ctx_buffer_sizes_are_valid(struct gk20a *g,
struct nvgpu_gr_global_ctx_buffer_desc *desc)
{
if ((desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE].size == 0U) ||
#ifdef CONFIG_NVGPU_VPR
(desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR].size == 0U) ||
#endif
(desc[NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP].size == 0U)) {
if (desc[NVGPU_GR_GLOBAL_CTX_PRIV_ACCESS_MAP].size == 0U) {
return false;
}
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if ((desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE].size == 0U)) {
return false;
}
#ifdef CONFIG_NVGPU_VPR
if ((desc[NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_PAGEPOOL_VPR].size == 0U) ||
(desc[NVGPU_GR_GLOBAL_CTX_ATTRIBUTE_VPR].size == 0U)) {
return false;
}
#endif
}
return true;
}
@@ -181,6 +189,19 @@ static int nvgpu_gr_global_ctx_buffer_vpr_alloc(struct gk20a *g,
{
int err = 0;
/*
* MIG supports only compute class.
* Allocate BUNDLE_CB, PAGEPOOL, ATTRIBUTE_CB and RTV_CB
* if 2D/3D/I2M classes(graphics) are supported.
*/
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
nvgpu_log(g, gpu_dbg_gr | gpu_dbg_mig,
"2D class is not supported "
"skip BUNDLE_CB, PAGEPOOL, ATTRIBUTE_CB "
"and RTV_CB");
return 0;
}
err = nvgpu_gr_global_ctx_buffer_alloc_vpr(g, desc,
NVGPU_GR_GLOBAL_CTX_CIRCULAR_VPR);
if (err != 0) {
@@ -208,22 +229,29 @@ static int nvgpu_gr_global_ctx_buffer_sys_alloc(struct gk20a *g,
{
int err = 0;
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_CIRCULAR);
if (err != 0) {
goto fail;
}
/*
* MIG supports only compute class.
* Allocate BUNDLE_CB, PAGEPOOL, ATTRIBUTE_CB and RTV_CB
* if 2D/3D/I2M classes(graphics) are supported.
*/
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_CIRCULAR);
if (err != 0) {
goto fail;
}
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_PAGEPOOL);
if (err != 0) {
goto fail;
}
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_PAGEPOOL);
if (err != 0) {
goto fail;
}
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_ATTRIBUTE);
if (err != 0) {
goto fail;
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_ATTRIBUTE);
if (err != 0) {
goto fail;
}
}
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
@@ -261,11 +289,13 @@ int nvgpu_gr_global_ctx_buffer_alloc(struct gk20a *g,
#endif
#ifdef CONFIG_NVGPU_DGPU
if (desc[NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER].size != 0U) {
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER);
if (err != 0) {
goto clean_up;
if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_MIG)) {
if (desc[NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER].size != 0U) {
err = nvgpu_gr_global_ctx_buffer_alloc_sys(g, desc,
NVGPU_GR_GLOBAL_CTX_RTV_CIRCULAR_BUFFER);
if (err != 0) {
goto clean_up;
}
}
}
#endif