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gpu: nvgpu: resolve misra 5.7 violation

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Rule 5.7 doesn't allow an identifier to be reused. This patch renames
variable "ops" to resolve this violation.

Jira NVGPU-6272

Change-Id: Ica8364a21d28dcf02d935a1b212e334b3f48c98a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471047
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vedashree Vidwans
2021-01-15 11:26:07 -08:00
committed by mobile promotions
parent 2cc8fdfa81
commit 2fa0e6fca1
1 changed files with 6 additions and 6 deletions
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12
drivers/gpu/nvgpu/hal/mc/mc_gm20b_fusa.c
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@@ -1,7 +1,7 @@
/* /*
* GM20B Master Control * GM20B Master Control
* *
* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -58,7 +58,7 @@ u32 gm20b_get_chip_details(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
u32 gm20b_mc_isr_nonstall(struct gk20a *g) u32 gm20b_mc_isr_nonstall(struct gk20a *g)
{ {
u32 ops = 0U; u32 nonstall_ops = 0U;
u32 mc_intr_1; u32 mc_intr_1;
u32 i; u32 i;
@@ -69,7 +69,7 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
} }
if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) { if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) {
ops |= g->ops.fifo.intr_1_isr(g); nonstall_ops |= g->ops.fifo.intr_1_isr(g);
} }
for (i = 0U; i < g->fifo.num_engines; i++) { for (i = 0U; i < g->fifo.num_engines; i++) {
@@ -81,19 +81,19 @@ u32 gm20b_mc_isr_nonstall(struct gk20a *g)
/* GR Engine */ /* GR Engine */
if (nvgpu_device_is_graphics(g, dev)) { if (nvgpu_device_is_graphics(g, dev)) {
ops |= g->ops.gr.intr.nonstall_isr(g); nonstall_ops |= g->ops.gr.intr.nonstall_isr(g);
} }
/* CE Engine */ /* CE Engine */
if (nvgpu_device_is_ce(g, dev) && if (nvgpu_device_is_ce(g, dev) &&
(g->ops.ce.isr_nonstall != NULL)) { (g->ops.ce.isr_nonstall != NULL)) {
ops |= g->ops.ce.isr_nonstall(g, nonstall_ops |= g->ops.ce.isr_nonstall(g,
dev->inst_id, dev->inst_id,
dev->pri_base); dev->pri_base);
} }
} }
return ops; return nonstall_ops;
} }
static int gm20b_mc_enable(struct gk20a *g, u32 mask, bool enable) static int gm20b_mc_enable(struct gk20a *g, u32 mask, bool enable)