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gpu: nvgpu: gsp sched: create and enable gsp virtual memory access

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Changes
- Initialize virtual memory for gsp. This space is used for creating
  queues for ctrl fifo. Also can be used to ro map sync-pt to this
  instance where gsp firmware can poll the sync-pt with sync-pt id.
- Enabled gsp context interface and written the instance block pointer
  to nxtctx register for the gsp firmware to access created virtual memory.
- Added required gsp registers for this feature.

NVGPU-8730
Bug 3770916

Change-Id: If538f615eca3f9b7840ffe2787826528b4808886
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2764649
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2022-08-24 09:38:28 +00:00
committed by mobile promotions
parent 6249220e09
commit 30e7a5e5ed
4 changed files with 31 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/gsp_scheduler/gsp_scheduler.c
View File

@@ -198,6 +198,11 @@ int nvgpu_gsp_sched_bootstrap_ns(struct gk20a *g)
goto de_init;
}
/* setup gsp ctx instance */
if (g->ops.gsp.falcon_setup_boot_config != NULL) {
g->ops.gsp.falcon_setup_boot_config(g);
}
status = gsp_sched_wait_for_init(g, gsp_sched, GSP_WAIT_TIME_MS);
if (status != 0) {
nvgpu_err(g, "gsp wait for basic init failed ");

31
drivers/gpu/nvgpu/hal/gsp/gsp_ga10b.c
View File

@@ -470,25 +470,24 @@ int ga10b_gsp_flcn_copy_from_emem(struct gk20a *g,
void ga10b_gsp_flcn_setup_boot_config(struct gk20a *g)
{
struct mm_gk20a *mm = &g->mm;
u32 inst_block_ptr;
nvgpu_log_fn(g, " ");
/* setup apertures - virtual */
gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
pgsp_fbif_transcfg_mem_type_physical_f() |
pgsp_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
pgsp_fbif_transcfg_mem_type_virtual_f());
/* setup apertures - physical */
gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
pgsp_fbif_transcfg_mem_type_physical_f() |
pgsp_fbif_transcfg_target_local_fb_f());
gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
pgsp_fbif_transcfg_mem_type_physical_f() |
pgsp_fbif_transcfg_target_coherent_sysmem_f());
gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
pgsp_fbif_transcfg_mem_type_physical_f() |
pgsp_fbif_transcfg_target_noncoherent_sysmem_f());
/*
* The instance block address to write is the lower 32-bits of the 4K-
* aligned physical instance block address.
*/
inst_block_ptr = nvgpu_inst_block_ptr(g, &mm->gsp.inst_block);
gk20a_writel(g, pgsp_falcon_nxtctx_r(),
pgsp_falcon_nxtctx_ctxptr_f(inst_block_ptr) |
pgsp_falcon_nxtctx_ctxvalid_f(1) |
nvgpu_aperture_mask(g, &mm->gsp.inst_block,
pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(),
pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(),
pgsp_falcon_nxtctx_ctxtgt_fb_f()));
}
int ga10b_gsp_queue_head(struct gk20a *g, u32 queue_id, u32 queue_index,

5
drivers/gpu/nvgpu/hal/init/hal_ga10b.c
View File

@@ -1950,6 +1950,11 @@ int ga10b_init_hal(struct gk20a *g)
nvgpu_set_enabled(g, NVGPU_SUPPORT_PMU_SUPER_SURFACE, true);
}
/*
* enable GSP VM for gsp scheduler firmware
*/
nvgpu_set_enabled(g, NVGPU_SUPPORT_GSP_VM, true);
/*
* ga10b bypasses the IOMMU since it uses a special nvlink path to
* memory.

6
drivers/gpu/nvgpu/include/nvgpu/hw/ga10b/hw_pgsp_ga10b.h
View File

@@ -172,4 +172,10 @@
#define pgsp_falcon_ecc_status_uncorrected_err_emem_m() (U32(0x1U) << 13U)
#define pgsp_falcon_ecc_status_uncorrected_err_dcls_m() (U32(0x1U) << 11U)
#define pgsp_falcon_ecc_status_uncorrected_err_reg_m() (U32(0x1U) << 12U)
#define pgsp_falcon_nxtctx_r() (0x00110054U)
#define pgsp_falcon_nxtctx_ctxptr_f(v) ((U32(v) & 0xfffffffU) << 0U)
#define pgsp_falcon_nxtctx_ctxtgt_fb_f() (0x0U)
#define pgsp_falcon_nxtctx_ctxtgt_sys_coh_f() (0x20000000U)
#define pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f() (0x30000000U)
#define pgsp_falcon_nxtctx_ctxvalid_f(v) ((U32(v) & 0x1U) << 30U)
#endif